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*     FPGA SPICE Netlist    *
* Description: LUTs *
*    Author: Xifan TANG     *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:08 2018
 *
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***** Auto-generated LUT info: spice_model_name = lut6, size = 6 *****
.subckt lut6 in0 in1 in2 in3 in4 in5 out sram0 sram1 sram2 sram3 sram4 sram5 sram6 sram7 sram8 sram9 sram10 sram11 sram12 sram13 sram14 sram15 sram16 sram17 sram18 sram19 sram20 sram21 sram22 sram23 sram24 sram25 sram26 sram27 sram28 sram29 sram30 sram31 sram32 sram33 sram34 sram35 sram36 sram37 sram38 sram39 sram40 sram41 sram42 sram43 sram44 sram45 sram46 sram47 sram48 sram49 sram50 sram51 sram52 sram53 sram54 sram55 sram56 sram57 sram58 sram59 sram60 sram61 sram62 sram63 svdd sgnd
Xinv0_in0_no0 in0 lut_mux_in0_inv svdd sgnd inv size='4'
Xbuf4_in0 in0 lut_mux_in0 svdd sgnd tapbuf_level2_f4

Xinv0_in1_no0 in1 lut_mux_in1_inv svdd sgnd inv size='4'
Xbuf4_in1 in1 lut_mux_in1 svdd sgnd tapbuf_level2_f4

Xinv0_in2_no0 in2 lut_mux_in2_inv svdd sgnd inv size='4'
Xbuf4_in2 in2 lut_mux_in2 svdd sgnd tapbuf_level2_f4

Xinv0_in3_no0 in3 lut_mux_in3_inv svdd sgnd inv size='4'
Xbuf4_in3 in3 lut_mux_in3 svdd sgnd tapbuf_level2_f4

Xinv0_in4_no0 in4 lut_mux_in4_inv svdd sgnd inv size='4'
Xbuf4_in4 in4 lut_mux_in4 svdd sgnd tapbuf_level2_f4

Xinv0_in5_no0 in5 lut_mux_in5_inv svdd sgnd inv size='4'
Xbuf4_in5 in5 lut_mux_in5 svdd sgnd tapbuf_level2_f4

Xlut_mux sram0 sram1 sram2 sram3 sram4 sram5 sram6 sram7 sram8 sram9 sram10 sram11 sram12 sram13 sram14 sram15 sram16 sram17 sram18 sram19 sram20 sram21 sram22 sram23 sram24 sram25 sram26 sram27 sram28 sram29 sram30 sram31 sram32 sram33 sram34 sram35 sram36 sram37 sram38 sram39 sram40 sram41 sram42 sram43 sram44 sram45 sram46 sram47 sram48 sram49 sram50 sram51 sram52 sram53 sram54 sram55 sram56 sram57 sram58 sram59 sram60 sram61 sram62 sram63 out lut_mux_in0 lut_mux_in0_inv lut_mux_in1 lut_mux_in1_inv lut_mux_in2 lut_mux_in2_inv lut_mux_in3 lut_mux_in3_inv lut_mux_in4 lut_mux_in4_inv lut_mux_in5 lut_mux_in5_inv svdd sgnd lut6_mux_size64
.eom