# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs # Each job execute fpga_flow script on combination of architecture & benchmark # timeout_each_job is timeout for each job # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = [GENERAL] power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif [ARCHITECTURES] # arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml #arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml #arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif [SYNTHESIS_PARAM] bench0_top = test_modes bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v bench0_chan_width = 300 #[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] #fix_route_chan_width=300 #vpr_fpga_verilog_include_icarus_simulator= #vpr_fpga_verilog_formal_verification_top_netlist= #vpr_fpga_verilog_include_timing= #vpr_fpga_verilog_include_signal_init= #vpr_fpga_verilog_print_autocheck_top_testbench= #vpr_fpga_bitstream_generator= #vpr_fpga_verilog_print_user_defined_template= #vpr_fpga_verilog_print_report_timing_tcl= #vpr_fpga_verilog_print_sdc_pnr= #vpr_fpga_verilog_print_sdc_analysis= ##vpr_fpga_x2p_compact_routing_hierarchy= #end_flow_with_test= [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] min_route_chan_width=1.3 vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= vpr_fpga_verilog_include_timing= vpr_fpga_verilog_include_signal_init= vpr_fpga_verilog_print_autocheck_top_testbench= vpr_fpga_bitstream_generator= vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= #vpr_fpga_verilog_explicit_mapping= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test=