# Standard Configuration Example
[dir_path]
#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog
#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif
#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20
benchmark_dir = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/fpga_flow/benchmarks/fpga_spice_test_bench
odin2_path = /home/xitang/research/vtr_release/ODIN_II/odin_II.exe
cirkit_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc
abc_path = /home/xitang/research/ABC/abc70930/abc
abc_mccl_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc
abc_with_bb_support_path = /home/xitang/research/vtr_release/abc_with_bb_support/abc
mpack1_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack
m2net_path = /home/xitang/tangxifan-eda-tools/branches/scripts/m2net.pl
mpack2_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v2/mpack2
#vpr_path = /home/xitang/research/vtr_release/vpr/vpr
vpr_path = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/vpr7_rram/vpr/vpr
rpt_dir = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/fpga_flow/results
ace_path = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/ace2/ace

[flow_conf]
flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr
#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr
vpr_arch = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm.xml # Use relative path under VPR folder is OK
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
#power_tech_xml = /home/xitang/research/vtr_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
power_tech_xml = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/power_tech_properties/tsmc40nm.xml # Use relative path under VPR folder is OK

[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate: 
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff