name: Cell Library Tests

# Run CI on push, PR, and weekly.
on:
  workflow_dispatch:
  pull_request:
  push:
    branches:
      - 'master'
  schedule:
    - cron: "0 0 * * 0 " # weekly

concurrency:
  group: ${{ github.workflow }}-${{ github.ref }}
  cancel-in-progress: true

# Multiple job to tests
jobs:
  # Test the RTL compilation compatibility
  verilog:
    name: RTL compilation and tests
    runs-on: ubuntu-22.04
    steps:
      - name: Cancel previous
        uses: styfle/cancel-workflow-action@0.12.1
        with:
          access_token: ${{ github.token }}
          
      - name: Checkout OpenFPGA repo
        uses: actions/checkout@v3

      - name: Install Dependencies
        run: |
          sudo bash .github/workflows/install_dependencies_run_ubuntu22p04.sh

      - name: Dump tool versions
        run: |
          iverilog -V
          vvp -V

      - name: Verilog compilation
        run: |
          cd openfpga_flow/openfpga_cell_library
          make compile_verilog