<!-- Architecture annotation for OpenFPGA framework This annotation supports the k6_N10_40nm.xml - General purpose logic block - K = 6, N = 10, I = 40 - Single mode - Routing architecture - L = 4, fc_in = 0.15, fc_out = 0.1 --> <openfpga_architecture> <technology_library> <device_library> <device_model name="logic" type="transistor"> <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/> <design vdd="0.9" pn_ratio="2"/> <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/> <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/> </device_model> <device_model name="io" type="transistor"> <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/> <design vdd="2.5" pn_ratio="3"/> <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/> <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/> </device_model> </device_library> <variation_library> <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/> <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/> </variation_library> </technology_library> <circuit_library> <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true"> <design_technology type="cmos" topology="inverter" size="1"/> <port type="input" prefix="in" size="1"/> <port type="output" prefix="out" size="1"/> <delay_matrix type="rise" in_port="in" out_port="out"> 10e-12 </delay_matrix> <delay_matrix type="fall" in_port="in" out_port="out"> 10e-12 </delay_matrix> </circuit_model> <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false"> <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/> <port type="input" prefix="in" size="1"/> <port type="output" prefix="out" size="1"/> <delay_matrix type="rise" in_port="in" out_port="out"> 10e-12 </delay_matrix> <delay_matrix type="fall" in_port="in" out_port="out"> 10e-12 </delay_matrix> </circuit_model> <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false"> <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/> <port type="input" prefix="in" size="1"/> <port type="output" prefix="out" size="1"/> <delay_matrix type="rise" in_port="in" out_port="out"> 10e-12 </delay_matrix> <delay_matrix type="fall" in_port="in" out_port="out"> 10e-12 </delay_matrix> </circuit_model> <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true"> <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/> <input_buffer exist="false"/> <output_buffer exist="false"/> <port type="input" prefix="in" size="1"/> <port type="input" prefix="sel" size="1"/> <port type="input" prefix="selb" size="1"/> <port type="output" prefix="out" size="1"/> <delay_matrix type="rise" in_port="in sel selb" out_port="out"> 10e-12 5e-12 5e-12 </delay_matrix> <delay_matrix type="fall" in_port="in sel selb" out_port="out"> 10e-12 5e-12 5e-12 </delay_matrix> </circuit_model> <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true"> <design_technology type="cmos"/> <input_buffer exist="false"/> <output_buffer exist="false"/> <port type="input" prefix="in" size="1"/> <port type="output" prefix="out" size="1"/> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> </circuit_model> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <design_technology type="cmos"/> <input_buffer exist="false"/> <output_buffer exist="false"/> <port type="input" prefix="in" size="1"/> <port type="output" prefix="out" size="1"/> <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> </circuit_model> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/> <!--mux2to1 subckt_name="mux2to1"/--> <pass_gate_logic circuit_model_name="TGATE"/> <port type="input" prefix="in" size="1"/> <port type="output" prefix="out" size="1"/> <port type="sram" prefix="sram" size="1"/> </circuit_model> <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true"> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="tap_buf4"/> <!--mux2to1 subckt_name="mux2to1"/--> <pass_gate_logic circuit_model_name="TGATE"/> <port type="input" prefix="in" size="1"/> <port type="output" prefix="out" size="1"/> <port type="sram" prefix="sram" size="1"/> </circuit_model> <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true"> <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="tap_buf4"/> <!--mux2to1 subckt_name="mux2to1"/--> <pass_gate_logic circuit_model_name="TGATE"/> <port type="input" prefix="in" size="1"/> <port type="output" prefix="out" size="1"/> <port type="sram" prefix="sram" size="1"/> </circuit_model> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v"> <design_technology type="cmos"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/> <pass_gate_logic circuit_model_name="TGATE"/> <port type="input" prefix="D" size="1"/> <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="output" prefix="Q" size="1"/> <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" /> </circuit_model> <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true"> <design_technology type="cmos"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/> <lut_input_inverter exist="true" circuit_model_name="INVTX1"/> <lut_input_buffer exist="true" circuit_model_name="buf4"/> <pass_gate_logic circuit_model_name="TGATE"/> <port type="input" prefix="in" size="6"/> <port type="output" prefix="out" size="1"/> <port type="sram" prefix="sram" size="64"/> </circuit_model> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v"> <design_technology type="cmos"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/> <pass_gate_logic circuit_model_name="TGATE"/> <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="D" size="1"/> <port type="output" prefix="Q" size="1"/> <port type="output" prefix="Qb" size="1"/> <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/> </circuit_model> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <design_technology type="cmos"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/> <pass_gate_logic circuit_model_name="TGATE"/> <port type="inout" prefix="pad" size="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/> <port type="input" prefix="outpad" size="1"/> <port type="output" prefix="inpad" size="1"/> </circuit_model> </circuit_library> <configuration_protocol> <organization type="scan_chain" circuit_model_name="sc_dff_compact"/> </configuration_protocol> <connection_block> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> </connection_block> <switch_block> <switch name="0" circuit_model_name="mux_2level_tapbuf"/> </switch_block> <routing_segment> <segment name="L4" circuit_model_name="chan_segment"/> </routing_segment> <pb_type_annotations> <!-- physical pb_type binding in complex block IO --> <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/> <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <!-- End physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block CLB --> <!-- physical mode will be the default mode if not specified --> <pb_type name="clb"> <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model --> <interconnect name="crossbar" circuit_model_name="mux_2level"/> </pb_type> <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/> <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="static_dff"/> <!-- End physical pb_type binding in complex block IO --> </pb_type_annotations> </openfpga_architecture> <openfpga_simulation_setting> <clock_setting> <operating frequency="200e6" num_cycles="auto" slack="0.2"/> <programming frequency="10e6"/> </clock_setting> <simulator_option> <operating_condition temperature="25"/> <output_log verbose="false" captab="false"/> <accuracy type="abs" value="1e-13"/> <runtime fast_simulation="true"/> </simulator_option> <monte_carlo num_simulation_points="2"/> <measurement_setting> <slew> <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/> <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/> </slew> <delay> <rise input_thres_pct="0.5" output_thres_pct="0.5"/> <fall input_thres_pct="0.5" output_thres_pct="0.5"/> </delay> </measurement_setting> <stimulus> <clock> <rise slew_type="abs" slew_time="20e-12" /> <fall slew_type="abs" slew_time="20e-12" /> </clock> <input> <rise slew_type="abs" slew_time="25e-12" /> <fall slew_type="abs" slew_time="25e-12" /> </input> </stimulus> </openfpga_simulation_setting>