# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr

[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
# Yosys script parameters
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v
yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
# VPR parameters
# Use a fixed routing channel width to save runtime
vpr_route_chan_width=300

[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml

[BENCHMARKS]
# Official benchmarks from VTR benchmark release
# Comment out due to high runtime 
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/bgm.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v
# Failed due to an unknown error in VPR netlist parser
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v
# Require many different DPRAM modules to be added (each has a different address and data width)
#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v
# Require many different DPRAM modules to be added (each has a different address and data width)
#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v
# Require many different DPRAM modules to be added (each has a different address and data width)
#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mcml.v
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v
bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v
bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v
bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/or1200.v
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v
bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v
bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v
# Comment out due to high runtime 
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v
# Additional benchmarks after VTR benchmark release
#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v
#bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/spree.v
#bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v

[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
# Benchmark ch_intrinsics
bench0_top = bgm
bench1_top = RLE_BlobMerging
bench2_top = paj_boundtop_hierarchy_no_mem
bench3_top = memset
bench4_top = diffeq_paj_convert
bench5_top = diffeq_f_systemC
bench6_top = LU8PEEng
bench7_top = LU32PEEng
bench8_top = mcml
bench9_top = mkDelayWorker32B
bench10_top = mkPktMerge
bench11_top = mkSMAdapter4B
bench12_top = or1200_flat
bench13_top = paj_raygentop_hierarchy_no_mem
bench14_top = sha1
bench15_top = sv_chip0_hierarchy_no_mem
bench16_top = sv_chip1_hierarchy_no_mem
bench17_top = sv_chip2_hierarchy_no_mem
bench18_top = sv_chip3_hierarchy_no_mem
bench19_top = arm_core
bench20_top = system
bench21_top = LU64PEEng

[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=