# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 200*60
fpga_flow=yosys_vpr

[ARCHITECTURES]
#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml

[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/adder/adder.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/arbiter/arbiter.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/bar/bar.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/cavlc/cavlc.v
bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/ctrl/ctrl.v
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/dec/dec.v
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/div/div.v
# This benchmark is failing -> debug ongoing
#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/hyp/hyp.v
bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/i2c/i2c.v
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/int2float/int2float.v
bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/log2/log2.v
bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/max/max.v
# This benchmark is commented because of its runtime
#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/mem_ctrl/mem_ctrl.v
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/multiplier/multiplier.v
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/priority/priority.v
bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/router/router.v
bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/sin/sin.v
bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/sqrt/sqrt.v
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/square/square.v
bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/voter/voter.v

[SYNTHESIS_PARAM]
bench0_top = adder
bench1_top = arbiter
bench2_top = bar
bench3_top = cavlc
bench4_top = ctrl
bench5_top = dec
bench6_top = div
#bench7_top = hyp 
bench8_top = i2c
bench9_top = int2float
bench10_top = log2
bench11_top = max
bench12_top = mem_ctrl
bench13_top = multiplier
bench14_top = priority
bench15_top = router
bench16_top = sin
bench17_top = sqrt
bench18_top = square
bench19_top = voter

#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
#fix_route_chan_width=300
#vpr_fpga_verilog_include_icarus_simulator=
#vpr_fpga_verilog_formal_verification_top_netlist=
#vpr_fpga_verilog_include_timing=
#vpr_fpga_verilog_include_signal_init=
#vpr_fpga_verilog_print_autocheck_top_testbench=
#vpr_fpga_bitstream_generator=
#vpr_fpga_verilog_print_user_defined_template=
#vpr_fpga_verilog_print_report_timing_tcl=
#vpr_fpga_verilog_print_sdc_pnr=
#vpr_fpga_verilog_print_sdc_analysis=
##vpr_fpga_x2p_compact_routing_hierarchy=
#end_flow_with_test=

[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
min_route_chan_width=1.3
#vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
#vpr_fpga_verilog_print_report_timing_tcl=
#vpr_fpga_verilog_print_sdc_pnr=
#vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_verilog_explicit_mapping=
vpr_fpga_x2p_compact_routing_hierarchy=
# If you wish to run Modelsim verification in batch, turn on the ini file outputting
vpr_fpga_verilog_print_simulation_ini=
# If you wish to run Modelsim verification in batch, turn off running iVerilog at the end of the flow
#end_flow_with_test=