echo Number of clock cycles in simulation: 7
echo Simulation progress: 0 Finish, 21 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/top_tb/example_1_top.sp -o ./spice_test_example_1/results/example_1_top.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 1 Finish, 20 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/grid_tb/example_1_grid1_1_grid_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_grid_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 2 Finish, 19 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/hardlogic_tb/example_1_grid1_1_hardlogic_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_hardlogic_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 3 Finish, 18 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/lut_tb/example_1_grid1_1_lut_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_lut_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 4 Finish, 17 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb1_1_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_1_sb_testbench.lis 
echo Number of clock cycles in simulation: 2
echo Simulation progress: 5 Finish, 16 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb1_0_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_0_sb_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 6 Finish, 15 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb0_1_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_1_sb_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 7 Finish, 14 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb0_0_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_0_sb_testbench.lis 
echo Number of clock cycles in simulation: 2
echo Simulation progress: 8 Finish, 13 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cby1_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cby1_1_cb_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 9 Finish, 12 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cby0_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cby0_1_cb_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 10 Finish, 11 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cbx1_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_1_cb_testbench.lis 
echo Number of clock cycles in simulation: 2
echo Simulation progress: 11 Finish, 10 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cbx1_0_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_0_cb_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 12 Finish, 9 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb1_1_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_1_sbmux_testbench.lis 
echo Number of clock cycles in simulation: 2
echo Simulation progress: 13 Finish, 8 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb1_0_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_0_sbmux_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 14 Finish, 7 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb0_1_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_1_sbmux_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 15 Finish, 6 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb0_0_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_0_sbmux_testbench.lis 
echo Number of clock cycles in simulation: 2
echo Simulation progress: 16 Finish, 5 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cby1_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cby1_1_cbmux_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 17 Finish, 4 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cby0_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cby0_1_cbmux_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 18 Finish, 3 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cbx1_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_1_cbmux_testbench.lis 
echo Number of clock cycles in simulation: 2
echo Simulation progress: 19 Finish, 2 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cbx1_0_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_0_cbmux_testbench.lis 
echo Number of clock cycles in simulation: 7
echo Simulation progress: 20 Finish, 1 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/pb_mux_tb/example_1_grid1_1_pbmux_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_pbmux_testbench.lis 
echo Simulation progress: 21 Finish, 0 to go, total 21