# Tutorial introduction

OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.<br />
Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.<br /><br />
These tutorials are organized as follow:
* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md)
* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md)
* Architecture modification

## Folder organization

OpenFPGA repository is organized as follow:
* **abc**: open source synthesys tool
* **ace2**: abc extension generating .act files
* **vpr7_x2p**: sources of modified vpr
* **yosys**: opensource synthesys tool
* **fpga_flow**: scripts and dependencies to run the complete flow

## Tips and informations

Some keywords will be used during this tutorial:
* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path