----------------------------------- Summary ------------------------------------ Circuit: /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes Architecture: k6_N10_sram_chain_HC_template.xml Technology (nm): 45 Voltage: 0.90 Temperature: 85 Critical Path: 5.8141e-09 Size of FPGA: 2 x 2 Channel Width: 200 ----------------------------------- Warnings ----------------------------------- No transistor counter function for BLIF model: .frac_lut6 No transistor counter function for BLIF model: .subckt adder No transistor counter function for BLIF model: .subckt shift Attempted to search for a transistor with a capacitance smaller than the smallest in the technology file. No dynamic power defined for BLIF model: .subckt adder No leakage power defined for BLIF model: .subckt adder No dynamic power defined for BLIF model: .frac_lut6 No leakage power defined for BLIF model: .frac_lut6 No dynamic power defined for BLIF model: .subckt shift No leakage power defined for BLIF model: .subckt shift ------------------------------- Power Breakdown -------------------------------- Component Power (W) %-Total %-Dynamic Method Total 0.0002701 1 0.7897 Routing 0.0001289 0.4773 0.7668 Switch Box 2.212e-05 0.08191 0 Connection Box 0.0001068 0.3954 0.9256 Global Wires 0 0 -nan PB Types 8.066e-05 0.2986 0.6884 Primitives 4.913e-05 0.1819 0.8837 Interc Structures 8.866e-06 0.03283 0.5489 Buffers and Wires 2.266e-05 0.08389 0.3197 Other Estimation Methods 0 0 -nan Clock 6.051e-05 0.224 0.9736 ---------------------------- Power Breakdown by PB ----------------------------- This sections provides a detailed breakdown of power usage by PB (physical block). For each PB, the power is listed, which is the sum power of all instances of the block. It also indicates its percentage of total power (entire FPGA), as well as the percentage of its power that is dynamic (vs. static). It also indicates the method used for power estimation. The data includes: Modes: When a pb contains multiple modes, each mode is listed, with its power statistics. Bufs/Wires: Power of all local buffers and local wire switching (transistor-level estimation only). Interc: Power of local interconnect multiplexers (transistor- level estimation only) Description of Estimation Methods: Transistor Auto-Size: Transistor-level power estimation. Local buffers and wire lengths are automatically sized. This is the default estimation method. Transistor Specify-Size: Transistor-level power estimation. Local buffers and wire lengths are only inserted where specified by the user in the architecture file. Pin-Toggle: Dynamic power is calculated using enery-per-toggle of the PB input pins. Static power is absolute. C-Internal: Dynamic power is calculated using an internal equivalent capacitance for PB type. Static power is absolute. Absolute: Dynamic and static power are absolutes from the architecture file. Sum of Children: Power of PB is only the sum of all child PBs; interconnect between the PB and its children is ignored. Ignore: Power of PB is ignored. Component Power (W) %-Total %-Dynamic Method io 0 0 -nan Ignore clb 8.066e-05 0.2986 0.6884 Transistor Auto-Size Bufs/Wires 1.43e-05 0.05294 0.2804 Interc: 8.462e-06 0.03133 0.542 crossbar0 3.015e-06 0.01116 0.5188 crossbar1 3.264e-06 0.01208 0.5568 crossbar2 1.076e-06 0.003984 0.5484 crossbar3 8.245e-07 0.003053 0.5364 crossbar4 0 0 -nan crossbar5 0 0 -nan clks 0 0 -nan carry_in 2.821e-07 0.001045 0.6112 fle 5.79e-05 0.2144 0.8106 Transistor Auto-Size Bufs/Wires 6.769e-06 0.02506 0.3446 Mode:fle_phy 3.361e-05 0.1244 0.9139 Interc: 0 0 -nan direct_clk 0 0 -nan mux1 0 0 -nan mux2 0 0 -nan frac_logic 3.388e-07 0.001254 0 Transistor Auto-Size Bufs/Wires 3.388e-07 0.001254 0 Interc: 0 0 -nan mux1 0 0 -nan mux2 0 0 -nan frac_lut6 0 0 -nan Transistor Auto-Size Bufs/Wires 0 0 -nan adder_phy 0 0 -nan Transistor Auto-Size Bufs/Wires 0 0 -nan ff_phy 3.327e-05 0.1232 0.9232 Transistor Auto-Size Bufs/Wires 0 0 -nan Mode:n2_lut5 1.741e-05 0.06444 0.7925 Interc: 0 0 -nan lut5inter 1.741e-05 0.06444 0.7925 Transistor Auto-Size Bufs/Wires 5.658e-07 0.002095 0.6977 Interc: 0 0 -nan complete1 0 0 -nan ble5 1.684e-05 0.06235 0.7956 Transistor Auto-Size Bufs/Wires 0 0 -nan Mode:blut5 1.12e-05 0.04146 0.8091 Interc: 0 0 -nan flut5 1.12e-05 0.04146 0.8091 Transistor Auto-Size Bufs/Wires 2.007e-07 0.000743 0.7628 Interc: 2.646e-07 0.0009797 0.684 mux1 2.646e-07 0.0009797 0.684 lut5 1.655e-06 0.006127 0.2417 Transistor Auto-Size Bufs/Wires 0 0 -nan Mode:wire 0 0 -nan Interc: 0 0 -nan complete:lut5 0 0 -nan Mode:lut5 1.655e-06 0.006127 0.2417 Interc: 0 0 -nan lut 1.655e-06 0.006127 0.2417 Transistor Auto-Size Bufs/Wires 0 0 -nan ff 9.079e-06 0.03361 0.9173 Transistor Auto-Size Bufs/Wires 0 0 -nan Mode:arithmetic 5.641e-06 0.02088 0.7689 Interc: 0 0 -nan arithmetic 5.641e-06 0.02088 0.7689 Transistor Auto-Size Bufs/Wires 3.732e-07 0.001382 0.7081 Interc: 1.399e-07 0.0005179 0.708 sumout 1.399e-07 0.0005179 0.708 lut4 7.913e-07 0.00293 0 Transistor Auto-Size Bufs/Wires 0 0 -nan Mode:wire 0 0 -nan Interc: 0 0 -nan complete:lut4 0 0 -nan Mode:lut4 7.913e-07 0.00293 0 Interc: 0 0 -nan lut 7.913e-07 0.00293 0 Transistor Auto-Size Bufs/Wires 0 0 -nan adder 0 0 -nan Transistor Auto-Size Bufs/Wires 0 0 -nan ff 4.336e-06 0.01606 0.9163 Transistor Auto-Size Bufs/Wires 0 0 -nan Mode:n1_lut6 0 0 -nan Interc: 0 0 -nan ble6 0 0 -nan Transistor Auto-Size Bufs/Wires 0 0 -nan Interc: 0 0 -nan mux1 0 0 -nan lut6 0 0 -nan Transistor Auto-Size Bufs/Wires 0 0 -nan Mode:wire 0 0 -nan Interc: 0 0 -nan complete:lut6 0 0 -nan Mode:lut6 0 0 -nan Interc: 0 0 -nan lut 0 0 -nan Transistor Auto-Size Bufs/Wires 0 0 -nan ff 0 0 -nan Transistor Auto-Size Bufs/Wires 0 0 -nan Mode:shift_register 1.134e-07 0.0004199 0.7826 Interc: 0 0 -nan ble_shift 1.134e-07 0.0004199 0.7826 Transistor Auto-Size Bufs/Wires 1.134e-07 0.0004199 0.7826 Interc: 0 0 -nan direct3 0 0 -nan ff 0 0 -nan Transistor Auto-Size Bufs/Wires 0 0 -nan