# Standard Configuration Example
[dir_path]
script_base = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/scripts/
benchmark_dir = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
yosys_path = /home/travis/build/LNIS-Projects/OpenFPGA/yosys/yosys
odin2_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
cirkit_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/cirkit
abc_path = /home/travis/build/LNIS-Projects/OpenFPGA/yosys/yosys-abc
abc_mccl_path = /home/travis/build/LNIS-Projects/OpenFPGA/abc_with_bb_support/abc
abc_with_bb_support_path = /home/travis/build/LNIS-Projects/OpenFPGA/abc_with_bb_support/abc
mpack1_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/mpack1
m2net_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/m2net
mpack2_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/mpack2
vpr_path = /home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/vpr
rpt_dir = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/results
ace_path = /home/travis/build/LNIS-Projects/OpenFPGA/ace2/ace

[flow_conf]
flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
vpr_arch = /home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/ARCH/.travis_k6_N10_sram_chain_HC.xml # temporary path to the architecture
#vpr_arch = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/arch/fpga_spice/.travis_k6_N10_sram_chain_HC.xml # Path when Architecture will move
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK

[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate: 
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff