.model top
.inputs i_a i_b i_c clka clkb clkc clkd
.outputs o_d o_e o_f o_g o_h o_i

#Input logic
.names i_a i_b w_d
11 1

#Input latches
.latch i_a l_a re clka 0
.latch i_b l_b re clkb 0
.latch i_c l_c re clkc 0
.latch w_d l_d re clkd 0

#Internal logic
.names l_a l_b l_c l_d w_and
1111 1

#Output latches
.latch w_and l_e re clka 0
.latch w_and l_f re clkb 0
.latch w_and l_g re clkc 0
.latch w_and l_h re clkd 0

#Output logic
.names w_d o_d
1 1

.names l_e o_e
1 1

.names l_f o_f
1 1

.names l_g o_g
1 1

.names l_h o_h
1 1

.names w_d l_e l_f l_g l_h o_i
11111 1

.end