# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs # Each job execute fpga_flow script on combination of architecture & benchmark # timeout_each_job is timeout for each job # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml # Here, we use a fabric netlist generated by another task # to show case the correctness of testbench generator # Caution: You MUST run the task 'basic_tests/generate_fabric' # before this task!!! openfpga_fabric_verilog_netlist=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fabric_netlists.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=