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Final1.1

v0.1-alpha

v0.2-alpha

v0.3-alpha

v1.1.0

v1.1.525

v1.1.541

v1.2.0

Mono Color

• ca48841ae3 Pass in the OpenFPGA root dir chungshien-chai 2024-07-29 11:04:03 -0700
• 5f45d13bfd
  Merge branch 'master' into openfpga-overwrite-bits tangxifan 2024-07-29 16:22:02 +0800
• 61d4114b64 Updated Patch Count github-actions[bot] 2024-07-29 08:07:16 +0000
• 7f9dffec89
  Merge pull request #1760 from lnis-uofu/dependabot/submodules/yosys-960bca0 tangxifan 2024-07-29 16:06:55 +0800
• 3c547f2131
  Bump yosys from `610d27d` to `960bca0` dependabot[bot] 2024-07-29 06:09:43 +0000
• aa3608428e
  Merge 57cb496314 into 4a07a32902 chungshien 2024-07-28 19:53:29 -0700
• 3e3f089823 Get the filepath using definition under [OpenFPGA_SHELL] chungshien-chai 2024-07-28 19:24:48 -0700
• 0d9f1a3c6b Forward searching the config bit + some minor refactor chungshien-chai 2024-07-28 19:12:34 -0700
• 9882394c8b Use archfpga_throw chungshien-chai 2024-07-28 02:53:18 -0700
• ae5b9a3f72
  Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits chungshien 2024-07-28 02:52:18 -0700
• 22d7df5ffb Update doc chungshien-chai 2024-07-28 02:40:24 -0700
• 2a3d69aded Update code based on feedback chungshien-chai 2024-07-28 02:37:15 -0700
• 4a07a32902
  Merge pull request #1759 from lnis-uofu/patch_update tangxifan 2024-07-28 17:04:48 +0800
• ec4be3595b Updated Patch Count github-actions[bot] 2024-07-28 09:04:21 +0000
• f5051398b5
  Merge pull request #1758 from lnis-uofu/dependabot/submodules/yosys-610d27d tangxifan 2024-07-28 17:04:04 +0800
• cbe9a46f95 Format and update doc chungshien-chai 2024-07-28 00:02:20 -0700
• 933155b08f Update test flow chungshien-chai 2024-07-27 23:52:54 -0700
• 0ff0c3445e Update doc chungshien-chai 2024-07-26 13:43:31 -0700
• fbe5ae6bd3 Update test chungshien-chai 2024-07-26 02:18:08 -0700
• 9641aaf6c4 Update test chungshien-chai 2024-07-26 02:17:25 -0700
• 6974e1b7e7
  Merge branch 'master' into openfpga-overwrite-bits chungshien 2024-07-26 01:37:57 -0700
• e60777d23e Use Bitstream Setting XML chungshien-chai 2024-07-26 01:36:49 -0700
• 67bc1b569b
  Bump yosys from `118b282` to `610d27d` dependabot[bot] 2024-07-26 06:52:25 +0000
• aed082817e
  Merge pull request #1757 from lnis-uofu/patch_update tangxifan 2024-07-26 10:28:21 +0800
• b635d17358 Updated Patch Count github-actions[bot] 2024-07-26 02:07:52 +0000
• 4bf4a77861
  Merge pull request #1754 from lnis-uofu/dependabot/submodules/yosys-118b282 tangxifan 2024-07-26 10:07:28 +0800
• 2ef362d53d Init support overwriting bitstream chungshien-chai 2024-07-25 17:40:46 -0700
• f142c73a11
  Merge branch 'lnis-uofu:master' into master chungshien 2024-07-25 12:53:25 -0700
• 542d422911 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clkntwk2 tangxifan 2024-07-22 21:56:00 +0800
• cd9f533292
  Bump yosys from `28ebefd` to `118b282` dependabot[bot] 2024-07-22 06:13:18 +0000
• 0d82682a73
  Merge pull request #1753 from lnis-uofu/patch_update tangxifan 2024-07-21 11:35:44 +0800
• 9570726ab9 Updated Patch Count github-actions[bot] 2024-07-21 03:13:52 +0000
• ce17197614
  Merge pull request #1751 from lnis-uofu/dependabot/submodules/yosys-28ebefd tangxifan 2024-07-21 11:13:31 +0800
• df0d64ddb4
  Bump yosys from `b08688f` to `28ebefd` dependabot[bot] 2024-07-19 06:34:08 +0000
• 1513ea749b [core] supporting clk spine on the same direction tangxifan 2024-07-16 22:12:51 -0700
• 18d12109fb [core] fixed a critical bug where cb port name using index is not considered on clock network entry tangxifan 2024-07-16 17:42:21 -0700
• c1f46c448a [core] fixed a critical bug where clock network entry is on a CHANY tangxifan 2024-07-16 17:04:44 -0700
• cbd10e1222 [core] fixed a bug where tile module's global port is not derived from dedicated clock network tangxifan 2024-07-16 16:58:21 -0700
• f607987386 [core] patch the out-of-range in clock rr nodes tangxifan 2024-07-16 16:45:55 -0700
• c77dc475d6
  Bump yosys from `b08688f` to `49f5477` dependabot[bot] 2024-07-16 06:13:41 +0000
• fc58daa239
  Merge pull request #1748 from lnis-uofu/patch_update tangxifan 2024-07-10 16:58:40 -0700
• ab126d8cfc Updated Patch Count github-actions[bot] 2024-07-10 23:57:28 +0000
• 1b9356e05c
  Merge pull request #1747 from lnis-uofu/dependabot/submodules/yosys-b08688f tangxifan 2024-07-10 16:57:05 -0700
• 37b302b335
  Merge pull request #1746 from lnis-uofu/xt_clkntwk2 tangxifan 2024-07-10 16:56:47 -0700
• 0c99fcf6f4 [doc] format tangxifan 2024-07-10 15:07:57 -0700
• c96f899c53 [core] code format tangxifan 2024-07-10 15:07:26 -0700
• a390aad0b8 [doc] add new syntax tangxifan 2024-07-10 15:07:16 -0700
• e614ca7380 [test] use new syntax tangxifan 2024-07-10 15:03:27 -0700
• a4538fb25b [core] now supports to_pin in building clock network for internal driver tangxifan 2024-07-10 15:01:18 -0700
• b2fc47a12a [core] reworked i/o for clock network files tangxifan 2024-07-10 14:34:54 -0700
• 079e6f2fca [core] add new syntax to support from_pin and to_pin for internal driver in clock network tangxifan 2024-07-10 14:28:28 -0700
• 215de8eb93 [core] code format tangxifan 2024-07-10 14:17:22 -0700
• f5ba43e392 [core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench tangxifan 2024-07-10 14:16:24 -0700
• 977283dd34 [core] typo tangxifan 2024-07-10 14:12:49 -0700
• af996e563e [test] add a new test to validate reset generated by internal driver through programmable clock network tangxifan 2024-07-10 14:11:06 -0700
• 213914e4ac [core] code format tangxifan 2024-07-10 12:23:57 -0700
• 48e159dd8d [core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches tangxifan 2024-07-10 12:23:15 -0700
• c6dd33a965 [core] fixed a bug when annotating global nets on OPIN tangxifan 2024-07-10 11:59:25 -0700
• b6ff69faac [test] reworking the testcase to validate clock network with internal drivers tangxifan 2024-07-10 11:36:22 -0700
• dbe8e63f53 [test] remove unused files tangxifan 2024-07-10 10:15:47 -0700
• 77304164f4 [test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W tangxifan 2024-07-10 10:13:41 -0700
• 191a3d1c5e [test] update W tangxifan 2024-07-10 10:01:31 -0700
• 81fe722d98 [test] adjust W tangxifan 2024-07-09 23:49:01 -0700
• 66a77c8658
  Bump yosys from `dac5bd1` to `b08688f` dependabot[bot] 2024-07-10 06:25:00 +0000
• 96bdcc8b35 [core] code format tangxifan 2024-07-09 22:54:55 -0700
• 63f2a07c86 [test] typo tangxifan 2024-07-09 22:54:33 -0700
• 27e29f949c [core] fixed a bug where the pin idx of global net on rr graph is not well annotated tangxifan 2024-07-09 22:53:12 -0700
• a16b3df063 [test] update arch to allow clock access on CLB inputs tangxifan 2024-07-09 20:59:44 -0700
• 0f78803759 [core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs tangxifan 2024-07-09 20:47:15 -0700
• 43dbeafd44 [test] typo tangxifan 2024-07-09 20:27:28 -0700
• 9ce4b57363 [test] typo tangxifan 2024-07-09 20:25:39 -0700
• e5d146a67a [test] add new tests to validate rst on lut and clk on lut features tangxifan 2024-07-09 20:24:23 -0700
• 89e6a0483f [test] add a new benchmark to validate rst and clk on LUTs tangxifan 2024-07-09 18:45:33 -0700
• 38bb5aa906 [test] add a new benchmark to validate clock on LUT tangxifan 2024-07-09 18:42:39 -0700
• a155ea4b41
  Merge pull request #1743 from lnis-uofu/dependabot/submodules/yosys-dac5bd1 tangxifan 2024-07-09 16:15:21 -0700
• e3caff56ee
  Merge pull request #1745 from lnis-uofu/patch_update tangxifan 2024-07-09 16:14:57 -0700
• f0e168c2b3 Updated Patch Count github-actions[bot] 2024-07-09 21:54:39 +0000
• a2afdae0cc
  Merge pull request #1741 from lnis-uofu/xt_clkntwk2 tangxifan 2024-07-09 14:54:16 -0700
• f42884304a [doc] update clock network details tangxifan 2024-07-09 11:40:41 -0700
• 5efc9d0e00 [test] update golden outputs tangxifan 2024-07-08 23:24:16 -0700
• ce759d0780
  Bump vtr-verilog-to-routing from `6a4f0ca` to `ddc3ac4` dependabot[bot] 2024-07-09 06:08:29 +0000
• 092b8b038f [core] remove verbose out tangxifan 2024-07-08 22:23:37 -0700
• 04504e4d5d [core] code format tangxifan 2024-07-08 22:22:59 -0700
• 1cdb1c5995 [core] fixed a bug on calculating subtile pins tangxifan 2024-07-08 22:22:08 -0700
• 5cb104a5f6 [test] fixed a bug tangxifan 2024-07-08 22:04:40 -0700
• bf484dbc70 [doc] add perimeter cb examples on prog clk network tangxifan 2024-07-08 21:25:12 -0700
• 229adebe07 [doc] new option to write_fabric_verilog tangxifan 2024-07-08 21:06:12 -0700
• 41839bfd7a [test] typo tangxifan 2024-07-08 20:21:40 -0700
• 8a5c33b1d6 [doc] new option for perimeter cb tangxifan 2024-07-08 19:01:16 -0700
• 03c1c6f917 [test] code format tangxifan 2024-07-08 18:35:23 -0700
• c7d6c3ab61 [arch] now all the outputs of I/O can only on 1 side tangxifan 2024-07-08 18:34:13 -0700
• ad053cddca [test] code format tangxifan 2024-07-08 18:02:30 -0700
• fe06c2f2b1 [core] code format tangxifan 2024-07-08 16:18:58 -0700
• db459b0e87 [core] add verbose outputs tangxifan 2024-07-08 16:18:32 -0700
• e8f9deeeaf [core] fixed a critical bug on computing pin index for subtile in clock taps tangxifan 2024-07-08 16:12:20 -0700
• 6dde383a7f [core] debugging tangxifan 2024-07-08 16:00:18 -0700
• c30eafac9f [test] fixed a bug on clk ntwk arch where some io clocks are not tapped tangxifan 2024-07-08 15:26:16 -0700
• 8bca3d79be [core] fixed a bug where tap points of clock network cannot reach perimeter cb tangxifan 2024-07-08 15:17:24 -0700
• b50acacfba [test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles tangxifan 2024-07-08 15:09:31 -0700
• 549dc6e7e6 [lib] update vtr tangxifan 2024-07-08 13:39:55 -0700