tangxifan
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5741664580
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[Regression Test] Add test case for k4n4 bram architecture
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2020-09-22 12:23:56 -06:00 |
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tangxifan
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ddf999b6b9
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[Architecture] Add verilog HDL for dual-port BRAM 1k
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2020-09-22 12:23:28 -06:00 |
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tangxifan
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26fba4a94b
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[Architecture] Add openfpga architectue for k4n4 with bram blocks
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2020-09-22 12:22:59 -06:00 |
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tangxifan
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daf776b7b1
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[Architecture] Add k4n4 architecture with bram block for basic tests
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2020-09-22 12:22:32 -06:00 |
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tangxifan
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237fc2e636
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[Regression test] Deploy no local routing in basic tests to CI
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2020-09-22 11:49:16 -06:00 |
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tangxifan
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3bf94b8e34
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[Regression test] Remove no local routing from fpga verilog tests
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2020-09-22 11:48:19 -06:00 |
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tangxifan
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7ed9f76b06
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[Regression test] Move k4n4 no local routing to basic test
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2020-09-22 11:47:03 -06:00 |
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tangxifan
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2dea97afb6
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[Regression test] reduce runtime for k4n4 test in basic testing
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2020-09-22 11:45:29 -06:00 |
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tangxifan
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2881312637
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[Regression test] deploy k4 series test cases to CI
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2020-09-22 11:43:34 -06:00 |
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tangxifan
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ea4dd410b7
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[Regression Test] Add k4n4 fracturable lut test case to basic test
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2020-09-22 11:41:36 -06:00 |
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tangxifan
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dad19cac9a
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[Regression test] Add k4 series architecture: fracturable adder
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2020-09-22 11:39:18 -06:00 |
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tangxifan
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dd192a2f54
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[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
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2020-09-22 11:34:23 -06:00 |
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tangxifan
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7a6f5a06f7
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[Architecture] Add a k4n4 architecture with carry chain to quick test
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2020-09-22 11:33:56 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
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fba8dbe638
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Merge pull request #89 from LNIS-Projects/dev
Regression test & architecture updates
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2020-09-21 22:53:34 -06:00 |
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tangxifan
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aa5f5fc7e0
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[Architecture] Bring back pin equivalence for no local routing architecture
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2020-09-21 22:22:39 -06:00 |
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tangxifan
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26f1a5d9ec
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[OpenFPGA Tool] Bug fix for repacking no local routing architecture
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2020-09-21 22:22:03 -06:00 |
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tangxifan
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a8a269aa82
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[Architecture] Temporary patch for the no local routing architecture
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2020-09-21 19:51:23 -06:00 |
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tangxifan
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acf318f184
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[Regression test] Bug fix in test case fabric_chain
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2020-09-21 18:58:35 -06:00 |
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tangxifan
|
e4291eb27e
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[Regression Tests] Now use fixed device layout in test cases for best coverage
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2020-09-21 18:44:13 -06:00 |
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tangxifan
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7a57cc9cf4
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[Architecture] A new device layout to k4n4 to test untileable architecture
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2020-09-21 18:36:50 -06:00 |
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tangxifan
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2bbfcb5753
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[Architecture] Add a new device layout to k4n4 for testing tileable routing
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2020-09-21 18:34:31 -06:00 |
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tangxifan
|
e1c5947143
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[Architecture] Add auto layout and fixed layout to architectures
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2020-09-21 18:01:51 -06:00 |
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tangxifan
|
936a164eee
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[OpenFPGA flow] Add a new template script to use a fixed device layout
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2020-09-21 17:48:28 -06:00 |
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tangxifan
|
d7f8b3abad
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[Architecture] Add k4 N4 untilable architecture
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2020-09-21 17:44:37 -06:00 |
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tangxifan
|
a83bc3f75c
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[Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI
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2020-09-21 17:38:16 -06:00 |
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tangxifan
|
e9c0e90544
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[Architecture] Add a VPR architectue using fracturable LUT4
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2020-09-21 17:37:26 -06:00 |
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tangxifan
|
60f328a2ab
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[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
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2020-09-21 17:36:57 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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9a995d143e
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Merge pull request #88 from LNIS-Projects/tangxifan-patch-1
Update issue templates
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2020-09-20 19:43:16 -06:00 |
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tangxifan
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5d9228eb2e
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Update bug_report.md
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2020-09-20 17:24:29 -06:00 |
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tangxifan
|
defb5dea4b
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Update issue templates
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2020-09-20 17:08:07 -06:00 |
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tangxifan
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dc11e84f6a
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Merge pull request #87 from LNIS-Projects/dev
Transplant FPGA-SPICE to OpenFPGA
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2020-09-20 17:05:33 -06:00 |
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tangxifan
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c6ac02d210
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[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation
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2020-09-20 15:21:33 -06:00 |
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tangxifan
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e867e203f4
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[Documentation] Use release mode in Docker settings
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2020-09-20 15:00:56 -06:00 |
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tangxifan
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544c44fe46
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[FPGA-SPICE] Add VDD and VSS port to module definition
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2020-09-20 14:58:15 -06:00 |
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tangxifan
|
615a24999a
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[Documentation] Remove out-of-date description
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2020-09-20 14:45:33 -06:00 |
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tangxifan
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460fef5807
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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tangxifan
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222bc86cbf
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[FPGA-SPICE] Add auxiliary SPICE netlist writer
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2020-09-20 12:53:28 -06:00 |
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tangxifan
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06c0073a3e
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[FPGA-SPICE] Add SPICE writer for fpga top module
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2020-09-20 12:43:48 -06:00 |
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tangxifan
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1dfb3e06cc
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[FPGA-SPICE] add SPICE writer for logic blocks
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2020-09-20 12:38:24 -06:00 |
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tangxifan
|
5e78e91fdf
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[FPGA-SPICE] Add SPICE writer for routing blocks
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2020-09-20 12:27:48 -06:00 |
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tangxifan
|
0f25b52907
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[FPGA-Verilog] code format fix
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2020-09-20 12:18:22 -06:00 |
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tangxifan
|
2fae311c8e
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[FPGA-SPICE] Add SPICE writer for memories
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2020-09-20 12:14:34 -06:00 |
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tangxifan
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f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
|
6801d260e9
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[FPGA-SPICE] Add SPICE writer for LUT
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2020-09-20 11:58:11 -06:00 |
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tangxifan
|
0f9fce92b2
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[FPGA-SPICE] Add SPICE writer for routing multiplexers
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2020-09-20 11:49:02 -06:00 |
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tangxifan
|
c7e3d97d1b
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[FPGA-SPICE] Add supply voltage generator
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2020-09-20 11:19:06 -06:00 |
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tangxifan
|
15df9b3893
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[FPGA-SPICE] Add SPICE subcircuit writer
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2020-09-19 23:01:44 -06:00 |
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tangxifan
|
82e137cbe4
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[FPGA-SPICE] Add wire module SPICE writer
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2020-09-19 19:31:16 -06:00 |
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tangxifan
|
1b2762386c
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[FPGA-SPICE] Bug fix for essential gate netlist writing
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2020-09-19 16:52:30 -06:00 |
|
tangxifan
|
26a0a769ea
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[FPGA-SPICE] Split essential gate SPICE netlists into separated files
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2020-09-19 16:45:26 -06:00 |