tangxifan
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2c6780ab92
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add side mirror detection for RRSwitchBlock
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2019-06-04 13:01:22 -06:00 |
Baudouin Chauviere
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3da216f297
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correction Null issue for the flat model
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2019-05-28 14:15:24 -06:00 |
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tangxifan
|
4b852afeac
|
skip rotating mirror detection which is too time-consuming
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2019-05-25 23:41:46 -06:00 |
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tangxifan
|
ae0248fbc6
|
debugging SwitchBlock rotating
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2019-05-24 23:10:30 -06:00 |
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tangxifan
|
27b996337a
|
fixed a critical bug in Compact Verilog generation for SB/CBs
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2019-05-24 16:14:46 -06:00 |
AurelienUoU
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9c05a4fb0a
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-10 14:09:23 -06:00 |
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AurelienUoU
|
ff9b84d800
|
Bug fix in Icarus requirement
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2019-05-10 14:07:32 -06:00 |
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tangxifan
|
a9df922412
|
finish the identification on mirror switch and connection blocks
Verilog generator to be updated
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2019-05-09 21:31:39 -06:00 |
|
AurelienUoU
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42f20eda60
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Add the user matching for internal register in formal verification script generation
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2019-05-03 10:24:02 -06:00 |
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tangxifan
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46d44fa42a
|
Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |