tangxifan
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fcaff28e24
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[HDL] Add a new IO cell with config_done support
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2022-02-24 09:46:55 -08:00 |
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tangxifan
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a615c9d4e3
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[Test] Rename test cases
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2022-02-24 09:43:41 -08:00 |
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tangxifan
|
e443a4567d
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[Arch] Typo
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2022-02-23 22:09:26 -08:00 |
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tangxifan
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b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
|
cf31879b20
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[Test] Deploy new test to basic regression tests
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2022-02-23 16:03:56 -08:00 |
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tangxifan
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245c7b1e45
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[Test] Add a new test case to validate config enable signal in preconfigured testbenches
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2022-02-23 16:02:00 -08:00 |
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tangxifan
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e33ba667e4
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[Test] Add missing file
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2022-02-20 10:59:44 -08:00 |
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tangxifan
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f30de1085c
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[Test] Cover all the related testcase about bus group
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2022-02-19 23:33:16 -08:00 |
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tangxifan
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b4202f52b4
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[Test] debugging
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2022-02-19 23:26:29 -08:00 |
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tangxifan
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785bb1633d
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[Test] trying to see if we support busgroup per benchmark in task configuration file
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2022-02-19 23:23:36 -08:00 |
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tangxifan
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7645d5332d
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[Test] Update bug group examples on the big endian support
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2022-02-18 23:09:03 -08:00 |
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tangxifan
|
68644ea0f6
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[Test] Add the new test to basic regression tests
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2022-02-18 15:44:07 -08:00 |
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tangxifan
|
f0ce1e79a3
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[Test] Added a new test to validate bus group in full testbench
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2022-02-18 15:43:21 -08:00 |
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tangxifan
|
fe9e0ff977
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[Test] Add the new test to basic regression tests
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2022-02-18 15:38:53 -08:00 |
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tangxifan
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c897a64ad5
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[Script] Add a new example script to test full testbenches using bus group features
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2022-02-18 15:37:42 -08:00 |
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tangxifan
|
223575cf3e
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[Test] Added a new test for bus group on full testbenches
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2022-02-18 15:33:29 -08:00 |
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tangxifan
|
85c893c94c
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[Test] Add new test to basic regression tests
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2022-02-18 15:30:08 -08:00 |
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tangxifan
|
5ab84e1861
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[Test] Add a new test for bus group
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2022-02-18 15:29:33 -08:00 |
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tangxifan
|
b4d59fdd1e
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[Test] Update bus group file due to little and big endian conversion during yosys/vpr
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2022-02-18 15:02:08 -08:00 |
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tangxifan
|
36543f7f2f
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[Script] Support simplified rewriting for Yosys on output verilog
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2022-02-18 14:54:39 -08:00 |
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tangxifan
|
8ba3d06392
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[Test] Fixed bugs in simulation settings
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2022-02-18 12:36:22 -08:00 |
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tangxifan
|
a4d5172b7c
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[Test] Fixed bugs that causes VPR failed
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2022-02-18 12:31:29 -08:00 |
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tangxifan
|
43d852d8a1
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[Test] Add the bus group test case to basic regression tests
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2022-02-18 12:27:25 -08:00 |
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tangxifan
|
7176037bc4
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[Test] Added a new test about bus group
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2022-02-18 12:26:00 -08:00 |
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tangxifan
|
73e6ee964d
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[Script] Add a new example script showing how to use bus group features
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2022-02-18 12:25:34 -08:00 |
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tangxifan
|
f02f3c10d4
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[Test] Fix bugs on the remaining implicit verilog test cases
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2022-02-15 16:49:15 -08:00 |
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tangxifan
|
074811a612
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[Script] Now counter benchmarks should pass on the implicit verilog test case
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2022-02-15 16:47:14 -08:00 |
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tangxifan
|
1370be0817
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[Script] Fixing bugs
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2022-02-15 16:44:51 -08:00 |
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tangxifan
|
8be0868a3b
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[Test] Update test case which uses counter benchmarks: adding pin constraints
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2022-02-15 16:29:06 -08:00 |
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tangxifan
|
430580f138
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[HDL] Fix a typo
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2022-02-15 16:09:14 -08:00 |
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tangxifan
|
a7786efde1
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[HDL] Now dual-clock counter has only 1 reset pin
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2022-02-15 16:07:50 -08:00 |
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tangxifan
|
f002c79a61
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[Test] Adapt pin constraints due to changes in pin names
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2022-02-15 16:06:46 -08:00 |
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tangxifan
|
b533fd17d5
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[Test] Rework pin constraints that cause problems
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2022-02-15 15:41:16 -08:00 |
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tangxifan
|
9ef7ad64d8
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[Test] Simplify paths
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2022-02-15 15:35:21 -08:00 |
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tangxifan
|
7121513396
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[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work
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2022-02-15 15:21:08 -08:00 |
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tangxifan
|
74045fc7a1
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[Script] Fix a bug
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2022-02-14 23:11:42 -08:00 |
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tangxifan
|
2990eb7406
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[Script] Fixed a bug in task run when removing previous runs
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2022-02-14 22:54:16 -08:00 |
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tangxifan
|
d0fe8d96fa
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[Test] Update template scripts and assoicated test cases by offering more options
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2022-02-14 16:03:48 -08:00 |
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tangxifan
|
d667102a43
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[Test] Add new test case to regression tests
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2022-02-14 15:58:53 -08:00 |
|
tangxifan
|
70363effa4
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[Test] Add a new test to validate 8-bit counters using full testbenches
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2022-02-14 15:57:55 -08:00 |
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tangxifan
|
2fb1df11bb
|
[Script] Add a new example script
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2022-02-14 15:54:07 -08:00 |
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tangxifan
|
7ef808cbe4
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[Test] Update pin constraints for different counter benchmarks
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2022-02-14 15:28:03 -08:00 |
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tangxifan
|
570c1b10dc
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[Test] Add dedicated pin constraints for counter designs
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2022-02-14 13:54:48 -08:00 |
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tangxifan
|
85011824e2
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[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
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2022-02-14 13:15:55 -08:00 |
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tangxifan
|
6630c17c23
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[Test] Use preconfigured testbench template to run counter8 tests
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2022-02-14 13:07:31 -08:00 |
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tangxifan
|
da3f9ccb80
|
[Test] Truncating counter designs in each task
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2022-02-14 12:22:19 -08:00 |
|
tangxifan
|
0268814fc6
|
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
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2022-02-14 12:20:56 -08:00 |
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tangxifan
|
1d3c9ff192
|
[Script] Adapt python scripts to support include directory
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2022-02-01 13:55:25 -08:00 |
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tangxifan
|
27ac2fafe5
|
[Test] Add the new test case to regression tests
|
2022-02-01 13:45:46 -08:00 |
|
tangxifan
|
532af96243
|
[Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench
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2022-02-01 13:44:47 -08:00 |