9add82148f
refactored CI for split regression tests in terms of OpenFPGA tools
2020-07-27 17:05:46 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
60dd37e086
remove simulation settings from openfpga arch XML
...
update travis to split CI tests
fix errors in travis configuration
fixing travis errors in scripts
keep fixing travis
fix travis on build.sh
bug fixing in travis CI
bug fix in travis regression test run
fixing bugs in the travis scripts
bug fix in travis script: remove common.sh in regression test call
keep bug fixing in travis
2020-06-11 19:31:17 -06:00
8db257946c
remove backport in travis setup. The link is dead now. Plus we no longer need the backport for a newer version of cmake
2020-03-10 12:18:39 -06:00
dd3d5fb7da
Update travis to use cmake 3.16
2020-01-24 11:06:07 -07:00
8b8f09387a
add travis packages
2020-01-03 22:34:22 -05:00
0740684567
remove libs from cache list
2020-01-03 22:06:40 -05:00
0852ef33c3
remove caching for deps
2019-11-02 16:30:01 -06:00
495000c649
recover caching for libs
2019-11-01 21:37:17 -06:00
17f816effd
try to uncache libini
2019-11-01 21:26:22 -06:00
a9c02cd2a5
fix errors in travis
2019-11-01 20:32:40 -06:00
550df19ee2
use a stable cmake now
2019-11-01 20:26:29 -06:00
4d4ef1113d
give up iverilog on travis
2019-11-01 17:53:50 -06:00
1d78725d4d
add installation
2019-11-01 17:48:17 -06:00
9a37b66d53
move installation to a script
2019-11-01 17:39:30 -06:00
161664f253
try to comfort iverilog package extraction
2019-11-01 17:24:06 -06:00
2dc3a4eb1f
fixing bugs in iVerilog installation
2019-11-01 17:03:21 -06:00
5332588e82
retrying travis installation of iVerilog 10.3
2019-11-01 16:36:29 -06:00
b61b81b8d8
tuning iverilog version display
2019-11-01 15:29:08 -06:00
d4fedb76d7
revert to default iverilog of Ubuntu 18.04
2019-11-01 15:24:58 -06:00
000f93ffd7
try to fix travis bugs
2019-11-01 15:19:34 -06:00
480478e545
reorganizing travis
2019-11-01 15:12:08 -06:00
b53a9b13bf
update travis with installation
2019-11-01 14:03:55 -06:00
de0be72634
try to make travis install latest iVerilog
2019-11-01 13:25:29 -06:00
de78718724
remove unused gcc setting in travis
2019-10-30 20:07:32 -06:00
7eac8be475
try to upgrade travis OS linux for the latest iverilog
2019-10-30 20:04:20 -06:00
ca2b836128
temporary remove MacOS from travis. Will bring back when debugged
2019-10-25 22:13:48 -06:00
db9beec77c
try to fix Travis MacOS issue
2019-10-25 21:52:30 -06:00
fc2562fc6c
change travis to an older version of XCode/MacOS but rather stable
2019-10-25 13:08:10 -06:00
cb147c1180
try to fix MacOS in travisCI
2019-10-25 10:44:40 -06:00
a1cd1ea8b4
fix travis error for MacOS
2019-10-24 22:51:24 -06:00
0439476abe
Removed OSX allowed failure from travis
2019-09-01 00:08:14 -06:00
d13c6a32ff
Test travis cache
2019-08-31 20:45:54 -06:00
31c4d40e66
Updated cache directory variable
2019-08-31 20:00:44 -06:00
3ce63e6163
Added abc and yosys cache in travis
2019-08-31 15:26:14 -06:00
1a15b9efd4
update travis settings
2019-08-21 15:27:07 -06:00
5e156dc725
minor fix for OSX and update travis using ccache to speed up compilation
2019-08-21 15:25:36 -06:00
35ad4a87e5
add travis slack notification
2019-08-14 12:51:17 -06:00
3ad4a33751
update travis to use gcc8 and disable graphics for vpr when compile in osx
2019-06-07 22:38:21 -06:00
1b02428c04
change travis gcc and gxx setting
2019-06-07 22:25:55 -06:00
f5b6ee6adf
update travis configuration and clean up repository
2019-06-07 22:19:11 -06:00
eb72cb201c
Use debug cmake build type to avoid building error
2019-06-03 15:34:26 -06:00
6974a4618f
Test gcc6 cmake3.13
2019-06-03 14:53:52 -06:00
c87c349c75
Test gcc6/cmake3.5
2019-06-03 13:58:00 -06:00
f4b8c3cf25
Try another combination cmake/gcc
2019-06-03 13:45:34 -06:00
813470d459
Test Cmake fix
2019-06-03 10:31:44 -06:00
4523bd21e9
Update version of cmake causing trouble
2019-06-03 10:21:24 -06:00
8c9820e7ee
Test without Verilog verification to se impact in building errors
2019-05-16 09:48:06 -06:00
c4ccff4562
Move Verilog test in another script to avoid false failure
2019-05-16 09:05:30 -06:00
57d75520a6
Verilog verification with Travis
2019-05-15 15:57:05 -06:00
tangxifan
srtemp
Ganesh Gore
AurelienUoU