tangxifan
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63cb8d589d
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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tangxifan
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d9bd0a6cf3
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[test] disable clustering-routing result sync-up when calling vpr in example scripts
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2022-09-19 20:52:04 -07:00 |
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tangxifan
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dbacee8a0a
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[script] turn off equivalent for soft adder architecture as we do not expect any routing optimization
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2022-08-27 20:25:50 -07:00 |
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tangxifan
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e9d6e7e38a
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[engine] update vtr and enable more debugging info
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2022-08-27 19:12:43 -07:00 |
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tangxifan
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fae5e1dfdf
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[Script] Upgrade openfpga shell script with the new option '--embed_bitstream'
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2021-06-25 15:16:37 -06:00 |
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tangxifan
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4e3f589810
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[Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench'
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2021-06-09 13:53:28 -06:00 |
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tangxifan
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9adf94bfd3
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[Script] Update all the openshell scripts to deprecate 'write_verilog_testbench'
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2021-06-09 11:18:52 -06:00 |
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tangxifan
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744d87cb4e
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[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
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2021-02-26 09:34:52 -07:00 |
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tangxifan
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8853370c60
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[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
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2021-02-04 20:20:10 -07:00 |
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tangxifan
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d3397f6936
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[Script] Remove activity from bitstream setting example script
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2021-02-02 09:25:36 -07:00 |
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tangxifan
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7f14dfbe87
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[Script] Add example script to use bitstream setting
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2021-02-02 09:18:08 -07:00 |