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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 8b3e79766c add fast configuration option to fpga_verilog to speed up full testbench simulation 2020-06-11 19:31:12 -06:00
tangxifan 1e73fd6def create configuration frame example script 2020-06-11 19:31:10 -06:00