tangxifan
|
441de12936
|
adapt Fc in gsb connection builder to use VPR8 Fc builder
|
2020-03-06 14:43:12 -07:00 |
|
tangxifan
|
ee4d5e46a0
|
Merge branch 'refactoring' into dev
|
2020-03-05 21:25:36 -07:00 |
|
tangxifan
|
8d350ee22f
|
adapt tileable rr_graph edge builder to rr_graph object
|
2020-03-05 20:50:21 -07:00 |
|
tangxifan
|
328488f357
|
adapt chan rr node builder to use rr_graph obj
|
2020-03-05 20:15:16 -07:00 |
|
tangxifan
|
3e3a523926
|
Merge branch 'refactoring' into dev
|
2020-03-05 17:48:43 -07:00 |
|
tangxifan
|
5067dd846e
|
adapting channel rr_node builder for tileable rr_graph
|
2020-03-05 17:47:48 -07:00 |
|
tangxifan
|
850788eace
|
adapt tileable rr_graph node builder for rr_graph object
|
2020-03-05 17:15:49 -07:00 |
|
tangxifan
|
5dcffb1a6e
|
Merge branch 'refactoring' into dev
|
2020-03-05 15:36:16 -07:00 |
|
tangxifan
|
de62ce8872
|
add node builder for tileable rr_graph builder
|
2020-03-05 15:34:04 -07:00 |
|
tangxifan
|
646ee90937
|
bring tileable gsb builder for rr_graph online
|
2020-03-04 18:19:53 -07:00 |
|
tangxifan
|
4455615980
|
adapt tileable routing channel detail builder
|
2020-03-04 14:21:35 -07:00 |
|
tangxifan
|
6e83154703
|
move rr_gsb and rr_chan to tileable rr_graph builder
|
2020-03-04 14:14:28 -07:00 |
|
tangxifan
|
4b7d2221d1
|
adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr
|
2020-03-04 13:55:53 -07:00 |
|
tangxifan
|
524798799c
|
start adapting tileable rr_graph builder. Bring channel node detail data structure online
|
2020-03-04 11:21:34 -07:00 |
AurelienUoU
|
aed3b01800
|
Directlist extension bug fix
|
2020-03-04 09:09:06 -07:00 |
|
tangxifan
|
9f13d3bc23
|
Merge branch 'refactoring' into dev
|
2020-03-03 12:31:20 -07:00 |
|
tangxifan
|
7fcd27e000
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
|
tangxifan
|
3241d8bd37
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
|
tangxifan
|
037c7e5c43
|
adapt top-level function for analysis SDC writer
|
2020-03-02 17:58:44 -07:00 |
|
tangxifan
|
24f7416c71
|
adapt analysis SDC writer for grids
|
2020-03-02 17:15:01 -07:00 |
|
tangxifan
|
6474183539
|
adapt analysis SDC writer for routing modules
|
2020-03-02 14:29:58 -07:00 |
|
tangxifan
|
543cff58b9
|
start porting analysis SDC writer
|
2020-03-02 13:44:08 -07:00 |
|
tangxifan
|
7befcaba57
|
Merge branch 'refactoring' into dev
|
2020-03-02 11:22:58 -07:00 |
|
tangxifan
|
a17c14c363
|
clean-up command addition and add fabric bitstream building to sample script
|
2020-03-02 10:39:19 -07:00 |
|
tangxifan
|
9fe8ff51f9
|
Merge branch 'refactoring' into dev
|
2020-02-29 15:19:52 -07:00 |
|
tangxifan
|
aa66042dfb
|
move simulation setting annotation to a separated source file
|
2020-02-29 15:19:02 -07:00 |
ganeshgore
|
ae4b0a6f9c
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-02-29 14:40:33 -07:00 |
|
tangxifan
|
cf25f1f339
|
Merge branch 'refactoring' into dev
|
2020-02-29 13:30:00 -07:00 |
|
tangxifan
|
7b18f7cd09
|
now the auto select number of clocks in simulation is online
|
2020-02-29 13:29:16 -07:00 |
|
tangxifan
|
3807a940f4
|
fixed critical bugs in bitstream generation and now we pass microbenchmarks
|
2020-02-28 16:45:50 -07:00 |
|
tangxifan
|
9fd184e3ab
|
rm out-of-date script
|
2020-02-28 15:42:18 -07:00 |
|
tangxifan
|
05ebd77d7d
|
start debugging with micro benchmarks. Spot problem in local routing
|
2020-02-28 15:41:32 -07:00 |
|
tangxifan
|
a6c2d2c7d1
|
bug fixed for io location mapping
|
2020-02-28 14:46:01 -07:00 |
|
tangxifan
|
80bb2baae5
|
start verification and bug fixing
|
2020-02-28 14:29:01 -07:00 |
|
tangxifan
|
542fadaaae
|
allow users to use VPR critical path delay in OpenFPGA simulation
|
2020-02-28 12:10:27 -07:00 |
|
tangxifan
|
de8425874c
|
use user defined critical path delay in SDC generation
|
2020-02-28 11:24:39 -07:00 |
|
tangxifan
|
092e10afda
|
bring pnr sdc generator online and fixed minor bugs in bitstream writing
|
2020-02-28 11:14:50 -07:00 |
|
tangxifan
|
e45fa18c4c
|
adapt PnR SDC writer
|
2020-02-28 10:06:35 -07:00 |
|
tangxifan
|
89c51b70e3
|
split sdc option into two categories which will be called by different commands
|
2020-02-28 09:48:58 -07:00 |
|
tangxifan
|
fdcb982903
|
adapt pnr sdc grid writer
|
2020-02-27 21:06:33 -07:00 |
|
tangxifan
|
b4ed931ac6
|
adapt sdc routing writer
|
2020-02-27 20:35:56 -07:00 |
|
tangxifan
|
d136ac236f
|
adapt sdc memory utils
|
2020-02-27 19:39:57 -07:00 |
|
tangxifan
|
78476ca774
|
adapt sdc writer utils
|
2020-02-27 19:36:28 -07:00 |
|
tangxifan
|
8322b1623d
|
start porting SDC generator
|
2020-02-27 19:30:36 -07:00 |
|
tangxifan
|
fc509aa2c1
|
Merge branch 'refactoring' into dev
|
2020-02-27 18:03:21 -07:00 |
|
tangxifan
|
65c81e14b2
|
add simulation ini file writer
|
2020-02-27 18:01:47 -07:00 |
|
tangxifan
|
ae899f3b11
|
bug fixed for clock names
|
2020-02-27 16:51:55 -07:00 |
|
tangxifan
|
9b769cd8e4
|
bug fix for using renamed i/o names
|
2020-02-27 16:37:20 -07:00 |
|
tangxifan
|
b010fc1983
|
add warning to force formal_verification_top_netlist enabled
|
2020-02-27 13:28:21 -07:00 |
|
tangxifan
|
078f72320f
|
debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
|
2020-02-27 13:24:26 -07:00 |