tangxifan
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f833e0ec66
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add a flagship architecture using fracturable memory and dsp
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2020-08-17 17:49:51 -06:00 |
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tangxifan
|
1ca2829868
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update readme for vpr architecture naming
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2020-08-17 13:54:26 -06:00 |
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tangxifan
|
cadf29022e
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add README to explain the organization of regression tests
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2020-07-28 13:44:06 -06:00 |
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tangxifan
|
f33422d4d7
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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tangxifan
|
534c609e17
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add fixed layouts to a flagship architecture to test bitstream generation runtime
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2020-07-28 11:51:50 -06:00 |
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tangxifan
|
a156807559
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enrich basic regression tests to cover more critical microbenchmarks
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2020-07-27 19:47:43 -06:00 |
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tangxifan
|
5d83abb2cf
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bug fix in read architecture bitstream and regression tests
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2020-07-27 19:37:05 -06:00 |
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tangxifan
|
31e7a753a6
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-07-27 19:22:16 -06:00 |
ganeshgore
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747c062f86
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BugFix : Flow script accepts extra OpenFPGA arguments
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2020-07-27 18:10:43 -06:00 |
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tangxifan
|
50cc4dfba3
|
classify regression test to dedicated categories
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2020-07-27 17:18:59 -06:00 |
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tangxifan
|
5595ee9052
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refine the test case for load external arch bitstream
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2020-07-27 16:53:29 -06:00 |
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tangxifan
|
cec6bf0b6f
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add or2 microbenchmark for testing external arch bitstream
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2020-07-27 15:59:03 -06:00 |
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tangxifan
|
4174fbf77d
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add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |
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tangxifan
|
a3eba8acbe
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update task files using the new syntax on SHELL variables
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2020-07-27 15:25:49 -06:00 |
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tangxifan
|
615b557dc4
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-07-27 14:48:23 -06:00 |
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tangxifan
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dc7012d590
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update regression tests for split fabric_bitstream commands
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2020-07-27 14:24:48 -06:00 |
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ganeshgore
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45af056304
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TASK_NAME and TASK_DIR variables are avaialble in config file now
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2020-07-27 14:14:57 -06:00 |
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ganeshgore
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0e46e0d857
|
Updated task.conf format to have transparent shell variables
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2020-07-27 14:08:58 -06:00 |
|
tangxifan
|
177de90822
|
bug fix in example scripts
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2020-07-26 22:10:04 -06:00 |
|
tangxifan
|
f687774452
|
bug fix in template scripts
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2020-07-26 21:46:03 -06:00 |
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tangxifan
|
41a76126b9
|
add fabric bitstream writer to CI
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2020-07-26 21:44:42 -06:00 |
|
tangxifan
|
c87f6b75b9
|
add test case for FPGA-SPICE
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2020-07-24 19:12:35 -06:00 |
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tangxifan
|
020154b0cd
|
add depopulate crossbar test case
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2020-07-24 18:06:02 -06:00 |
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tangxifan
|
021fedbc12
|
update fabric key to synchronize with new module/instance naming
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2020-07-24 12:55:40 -06:00 |
|
tangxifan
|
fefcd88f14
|
update openfpga architecture README for power-gating
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2020-07-22 21:55:59 -06:00 |
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tangxifan
|
22159531c5
|
bug fix in power gating support of FPGA-Verilog
|
2020-07-22 20:21:38 -06:00 |
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tangxifan
|
ca867ea6fa
|
add power gate inverter test case (full testbench)
|
2020-07-22 20:09:52 -06:00 |
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tangxifan
|
87ef7f9f99
|
add power gate example architecture
|
2020-07-22 20:06:10 -06:00 |
|
tangxifan
|
8ade40713a
|
add missing architecture for CI
|
2020-07-22 14:07:39 -06:00 |
|
tangxifan
|
1a1c3885e7
|
use k6 n10 in mux designs to speed up CI
|
2020-07-22 13:54:09 -06:00 |
|
tangxifan
|
95c1fe61e1
|
use k6 n8 in mux design to speed up CI
|
2020-07-22 13:49:03 -06:00 |
|
tangxifan
|
f754c8af06
|
use k6_n10 architecture to reduce CI runtime
|
2020-07-22 13:45:55 -06:00 |
|
tangxifan
|
92c3449999
|
bug fix in the regression test due to benchmark changes
|
2020-07-22 13:17:05 -06:00 |
|
tangxifan
|
05dccadf21
|
bug fix in the testcases using yosys_vpr flow
|
2020-07-22 12:44:19 -06:00 |
|
tangxifan
|
7d39e136a4
|
enrich micro benchmarks
|
2020-07-22 12:33:52 -06:00 |
|
tangxifan
|
1d36de817f
|
adapt generate bitstream testcase to use yosys vpr flow
|
2020-07-22 12:24:34 -06:00 |
|
tangxifan
|
b96cdbf857
|
adapt preconfig test cases to use yosys_vpr flow
|
2020-07-22 12:23:39 -06:00 |
|
tangxifan
|
d8804f4ec1
|
deploy yosys_vpr flow to basic regression tests
|
2020-07-22 12:21:59 -06:00 |
|
tangxifan
|
f4e77e3bad
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-07-22 12:09:34 -06:00 |
|
ganeshgore
|
3b6cd885f3
|
BugFix: Fixed yosys_vpr with openFPGA_Shell
|
2020-07-22 11:57:04 -06:00 |
|
tangxifan
|
eb070694b5
|
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
|
2020-07-15 17:52:41 -06:00 |
|
tangxifan
|
ca90f337a7
|
add fast configuration chain test case
|
2020-07-15 11:56:47 -06:00 |
|
tangxifan
|
66a50742fc
|
use configuration chain in the k4k4 test case to speed up CI
|
2020-07-15 11:56:11 -06:00 |
|
tangxifan
|
1c5bede282
|
update arch file with device technology binding information
|
2020-07-13 19:06:51 -06:00 |
|
tangxifan
|
824b56f14c
|
fabric key can now accept instance name only; decoders are no longer part of the key
|
2020-07-06 16:42:33 -06:00 |
|
tangxifan
|
1e6955aaa4
|
rename arch directory to be clear for its usage
|
2020-07-04 19:13:28 -06:00 |
|
tangxifan
|
f9a2bb0490
|
Reorganize task directory
|
2020-07-04 19:06:41 -06:00 |
|
tangxifan
|
4f8260a7ba
|
remove obselete codes and update regression tests
|
2020-07-04 17:31:34 -06:00 |
|
tangxifan
|
1c634e4600
|
add missing task file for generate bitstream test case
|
2020-07-02 17:24:51 -06:00 |
|
tangxifan
|
adea6fcec4
|
add bitstream generation only test case to CI
|
2020-07-02 16:31:22 -06:00 |