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OpenFPGA
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3 Commits

Author SHA1 Message Date
tangxifan 9761d13eef update microbenchmark and2 module name 2020-04-20 13:37:39 -06:00
tangxifan 32ed609238 update micro benchmark set and regression tests using them 2020-04-19 12:49:07 -06:00
tangxifan 59ea0a6ad5 add implicit verilog test case to Travis CI 2020-04-12 20:00:20 -06:00