Commit Graph

5 Commits

Author SHA1 Message Date
tangxifan f558405887 ported verilog testbench generator online. Split from fabric generator. Testing to be done 2020-02-27 12:33:09 -07:00
tangxifan e37ac8a098 add grid module Verilog writer 2020-02-16 16:04:41 -07:00
tangxifan c6c3ef71f3 adapt all the Verilog submodule writers and bring it onlien 2020-02-16 13:35:18 -07:00
tangxifan bf54be3d00 add option data structure for FPGA Verilog 2020-02-15 21:39:47 -07:00
tangxifan da79ef687c add missing files 2020-02-15 20:54:37 -07:00