2 Commits

Author	SHA1	Message	Date
Aram Kostanyan	6a4cc340a3	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
tangxifan	b72d4bd807	[Test] Update test case for 1kbit DPRAM architectures	2021-04-28 11:28:53 -06:00