3 Commits

Author	SHA1	Message	Date
Aram Kostanyan	6a4cc340a3	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
komaljaved-rs	be14e4f448	added design_variables.yml	2021-07-01 16:31:42 +05:00
komaljaved-rs	6559f71082	added ci_scripts	2021-07-01 15:07:37 +05:00