tangxifan
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8aa2647878
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[Script] Bug fix in slow clock frequency in shift register chain contraints
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2021-10-06 16:49:01 -07:00 |
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tangxifan
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dc5aedc393
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[Script] Correct naming for clocks in shifter register chain defined in simulation setting files
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2021-10-06 13:36:35 -07:00 |
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tangxifan
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169bb5fa45
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[Script] Add an example simulation setting file with a fixed clock frequency for shift registers
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2021-10-06 11:58:50 -07:00 |
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tangxifan
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ff6f7e80f6
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[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers
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2021-10-01 16:52:06 -07:00 |
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tangxifan
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7b010ba0f4
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[Engine] Support programming shift register clock in XML syntax
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2021-10-01 11:00:38 -07:00 |
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tangxifan
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77896379e2
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[Arch] Add simulation setting for 8-clock architectures
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2021-02-22 11:10:03 -07:00 |
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tangxifan
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16debe49f6
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[Arch] Add more comments on the 4 clock simulation setting file
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2021-02-22 11:04:34 -07:00 |
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tangxifan
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89f9d24d32
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[Flow] Update simulation settings for multiple clock to allow unique clock port name
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2021-01-15 10:35:43 -07:00 |
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tangxifan
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dbed04b53b
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[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
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2021-01-14 15:42:21 -07:00 |
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tangxifan
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923f3a3401
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[Flow] Add an example simulation settings for a 4-clock FPGA fabric
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2021-01-13 17:29:39 -07:00 |
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tangxifan
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cb09896f23
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add example simulation setting for openfpga flow
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2020-06-11 19:31:15 -06:00 |