tangxifan
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fd580bb36f
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[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
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2021-06-22 11:45:23 -06:00 |
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tangxifan
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f9e66e1bae
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[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
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2021-06-21 15:27:12 -06:00 |
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tangxifan
|
fce84e564d
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[Script] Patch on missing string to show in error message
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2021-06-18 11:20:35 -06:00 |
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tangxifan
|
0e01177cf0
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[Script] Now openfpga flow script output detailed error message when task is not found
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2021-06-18 11:01:45 -06:00 |
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tangxifan
|
781880ed93
|
[Script] Add tolerance options to check qor script
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2021-03-23 12:26:33 -06:00 |
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tangxifan
|
adfbd28a7a
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[Script] Add a simple QoR checker
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2021-03-23 11:06:16 -06:00 |
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tangxifan
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e1f8b252b1
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-16 20:05:21 -06:00 |
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tangxifan
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090f483a11
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[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
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2021-03-16 16:45:57 -06:00 |
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tangxifan
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b42541d84e
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[Flow] Support multiple iterations in rewriting yosys scripts
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2021-03-10 14:10:35 -07:00 |
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tangxifan
|
035043d0d8
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[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
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2021-03-10 13:36:11 -07:00 |
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tangxifan
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5d46537b5b
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[Script] Allow users to specify custom post-synthesis verilog for simulation
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2021-03-10 11:45:55 -07:00 |
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tangxifan
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aafd87c3f9
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[Flow] Update flow-run to support custom yosys rewrite scripts
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2021-03-10 11:36:29 -07:00 |
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tangxifan
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131643dcc0
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[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
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2021-03-08 21:08:55 -07:00 |
ganeshgore
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b860722893
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Fixed parameter ys_rewrite_params name bug
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2021-03-08 10:34:39 -07:00 |
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ganeshgore
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52de55e7eb
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Merge branch 'master' into ganesh_dev
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2021-03-08 10:15:06 -07:00 |
|
Ganesh Gore
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7a35811430
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[Flow] Yosys rewrite support
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2021-03-08 00:35:47 -07:00 |
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Ganesh Gore
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67cd9a69b7
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[Flow] Extended yosys variable subtitution
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2021-03-08 00:21:07 -07:00 |
Lalit Sharma
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6a1ce01084
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Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
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2021-03-07 22:02:11 -08:00 |
|
Lalit Sharma
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0cbad747a1
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Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
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2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
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817729ac86
|
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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2021-03-01 22:31:15 -08:00 |
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tangxifan
|
d85d6e964e
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Merge pull request #227 from watcag/master
Standard-cell flow
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2021-02-17 10:11:34 -07:00 |
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tangxifan
|
a819375f69
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[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
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2021-02-16 16:53:13 -07:00 |
Tarachand Pagarani
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3a587f663a
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copy yosys output file in case power analysis setting is off
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2021-02-15 02:36:02 -08:00 |
Nachiket Kapre
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b4185f7e8c
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Merge branch 'master' of github.com:lnis-uofu/OpenFPGA
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2021-02-08 21:11:30 -05:00 |
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Nachiket Kapre
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2344cdcabc
|
merge
|
2021-02-08 21:11:28 -05:00 |
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tangxifan
|
1ce94040da
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Merge pull request #221 from lnis-uofu/flow_dev
[Flow] Support multi-user environment for running task
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2021-02-08 12:43:57 -07:00 |
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Ganesh Gore
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ede5f8ed58
|
[Flow] Support multi-user enviroment for running task
|
2021-02-07 22:11:04 -07:00 |
|
Ganesh Gore
|
6cdc31f073
|
[Flow] ACE is optional duign flow script
|
2021-02-03 19:07:48 -07:00 |
|
Ganesh Gore
|
df4a397470
|
[Cleanup] Removed deadcode
|
2021-02-03 10:35:14 -07:00 |
|
Ganesh Gore
|
0b82b6439b
|
[Regression] Upgraded runtime enviroment to python3.8
|
2021-01-26 16:40:45 -07:00 |
|
ganeshgore
|
289d9d2169
|
[Bugfix] Honors yosys_tmpl parameter in flow script
|
2020-12-03 12:24:24 -07:00 |
|
ganeshgore
|
59bd7d0f18
|
[Flow] Changed substitute to safe_sustitute option
|
2020-11-25 22:09:36 -07:00 |
|
ganeshgore
|
fefba0db59
|
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
|
2020-11-25 17:29:53 -07:00 |
|
ganeshgore
|
1554f583b7
|
[Flow] Now support explicit variable file for task
|
2020-11-25 17:22:41 -07:00 |
|
tangxifan
|
521accdc88
|
Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
|
2020-10-07 09:54:06 -06:00 |
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tangxifan
|
7b12c28e4f
|
Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
|
2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
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33bbe0ec48
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FLOW: fixed display flag
|
2020-10-06 20:52:28 -04:00 |
|
Andrew Lukefahr
|
d68427e47b
|
Fixed blif formatting bug
|
2020-10-06 20:46:50 -04:00 |
|
Andrew Lukefahr
|
2d92a1f1af
|
Edits to enable basic run_fpga_flow.py
|
2020-10-02 10:18:10 -04:00 |
|
tangxifan
|
dbd93e429d
|
now pro_blif.pl can accept customized clock name
|
2020-08-19 09:43:44 -06:00 |
|
ganeshgore
|
747c062f86
|
BugFix : Flow script accepts extra OpenFPGA arguments
|
2020-07-27 18:10:43 -06:00 |
|
ganeshgore
|
45af056304
|
TASK_NAME and TASK_DIR variables are avaialble in config file now
|
2020-07-27 14:14:57 -06:00 |
|
ganeshgore
|
0e46e0d857
|
Updated task.conf format to have transparent shell variables
|
2020-07-27 14:08:58 -06:00 |
|
ganeshgore
|
3b6cd885f3
|
BugFix: Fixed yosys_vpr with openFPGA_Shell
|
2020-07-22 11:57:04 -06:00 |
|
tangxifan
|
4f8260a7ba
|
remove obselete codes and update regression tests
|
2020-07-04 17:31:34 -06:00 |
|
ganeshgore
|
41585436c8
|
Added external_fabric_key_file key
|
2020-06-12 15:37:12 -06:00 |
|
ganeshgore
|
c1b73efa62
|
Added support for simulation setting file in the task flow
|
2020-06-10 23:12:30 -06:00 |
|
ganeshgore
|
a3103f6afe
|
BugFix : Relative path for refrence benchmark fixed
|
2020-04-25 20:16:17 -06:00 |
|
ganeshgore
|
9d1b3d6865
|
Fixed modelsim include references
|
2020-04-24 21:53:57 -06:00 |
|
ganeshgore
|
689c4a3e19
|
BugFix: The filename in the previous commit
|
2020-04-15 12:44:22 -06:00 |