tangxifan
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7ade48343c
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[Tool] Deprecate command 'write_verilog_testbench'
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2021-06-09 17:06:01 -06:00 |
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tangxifan
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97396eda2b
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[Tool] Add a new command 'write_simulation_task_info'
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2021-06-08 22:10:02 -06:00 |
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tangxifan
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d2275b971d
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[Tool] Add a new command 'write_preconfigured_testbench'
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2021-06-08 21:53:51 -06:00 |
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tangxifan
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8db19c7af9
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[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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2021-06-08 21:28:16 -06:00 |
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tangxifan
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ae6a46cd60
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[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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2021-06-03 15:41:11 -06:00 |
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tangxifan
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b9dab2baaf
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add exit codes to command execution in shell context
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2020-04-08 16:18:05 -06:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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da79ef687c
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add missing files
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2020-02-15 20:54:37 -07:00 |