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riscv
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OpenFPGA
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tangxifan
53da5d49fe
[Arch] Correct XML syntax errors
2021-09-22 15:48:14 -07:00
tangxifan
212c5bd642
[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
2021-09-22 15:04:19 -07:00