3 Commits

Author	SHA1	Message	Date
tangxifan	bba476fef4	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
tangxifan	13f591cacf	add new command to disable timing for configure ports of programmable modules	2020-06-11 19:31:06 -06:00
tangxifan	fc2b09514e	add configuration chain write to regression tests	2020-06-11 19:31:06 -06:00