4 Commits

Author	SHA1	Message	Date
tangxifan	e78643f108	add flatten routing test case to Travis CI	2020-04-12 20:06:40 -06:00
tangxifan	59ea0a6ad5	add implicit verilog test case to Travis CI	2020-04-12 20:00:20 -06:00
ganeshgore	f6b3c5854a	Bugfix : ... + OpenFPGA template variables update + Default path for the verilog netlist	2020-04-11 16:45:22 -06:00
ganeshgore	7f98ecc8a6	OpenFPGA shell run test script template	2020-04-06 00:32:43 -06:00