tangxifan
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d0e05b3575
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[Lib] Now use pb_type in design constraints instead of physical tiles
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2021-01-16 21:35:43 -07:00 |
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tangxifan
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bb8e7e25c2
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[Tool] Start deploying design constraints in repack engine
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2021-01-16 21:27:12 -07:00 |
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tangxifan
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b86adabe69
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[Lib] Remove unused data storage from repack design constraints
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2021-01-16 21:14:52 -07:00 |
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tangxifan
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fa67517349
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[Tool] Add repack design constraints to openfpga command 'repack'
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2021-01-16 18:49:34 -07:00 |
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tangxifan
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706e84bb62
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[Lib] Bug fix in testing program
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2021-01-16 18:15:56 -07:00 |
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tangxifan
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67c54c4d3b
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[Lib] Bug fix in the repack design constraint lib
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2021-01-16 17:34:22 -07:00 |
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tangxifan
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ad7a54db1b
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[Tool] Add repack dc library to compilation
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2021-01-16 17:20:59 -07:00 |
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tangxifan
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9d80f1ab39
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[Lib] Add test program to the library of repack design constraints
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2021-01-16 17:18:42 -07:00 |
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tangxifan
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03b5bcc244
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[Lib] Add XML writer for repack design constraints
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2021-01-16 17:15:31 -07:00 |
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tangxifan
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2a7601fb7e
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[Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints
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2021-01-16 17:14:51 -07:00 |
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tangxifan
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f1bfa2ef8c
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[Lib] Add XML parser for repack design constraints
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2021-01-16 17:03:01 -07:00 |
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tangxifan
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8be12b6e82
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[Lib] Add example design constraint file
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2021-01-16 16:36:10 -07:00 |
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tangxifan
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a926c74ae5
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[Lib] Add CMake script to compile the repack design constraint library
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2021-01-16 16:35:46 -07:00 |
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tangxifan
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b57dc7b898
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[Lib] Add repack design constraint library
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2021-01-16 16:35:13 -07:00 |
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tangxifan
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8578c1ecac
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[Flow] Rename the design contraint file syntax
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2021-01-16 15:35:13 -07:00 |
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tangxifan
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9154cfdeec
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[Flow] Add comments for the design constraint file
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2021-01-16 15:34:01 -07:00 |
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tangxifan
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6ab0f71896
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[Test] Add an example of repack pin constraints file
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2021-01-16 14:38:39 -07:00 |
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tangxifan
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4f1d815d7b
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Merge pull request #173 from lnis-uofu/dev
Support Multiple Clock Definition in Testbench and SDC Generators
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2021-01-15 16:13:46 -07:00 |
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tangxifan
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b8e4675a3a
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[Tool] Add missing file
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2021-01-15 14:48:19 -07:00 |
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tangxifan
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c4d3e7c50c
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[Doc] Update documentation for the new XML syntax in simulation settings
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2021-01-15 12:30:26 -07:00 |
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tangxifan
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87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
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89f9d24d32
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[Flow] Update simulation settings for multiple clock to allow unique clock port name
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2021-01-15 10:35:43 -07:00 |
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tangxifan
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dbed04b53b
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[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
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2021-01-14 15:42:21 -07:00 |
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tangxifan
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3b5394b45f
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[Test] Now use dedicated simulation settings for the 4-clock architecture
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2021-01-14 15:40:16 -07:00 |
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tangxifan
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852f5bb72e
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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tangxifan
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923f3a3401
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[Flow] Add an example simulation settings for a 4-clock FPGA fabric
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2021-01-13 17:29:39 -07:00 |
Ashton Snelgrove
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effe86fb9e
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Remove pull request trigger
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2021-01-13 17:16:39 -07:00 |
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tangxifan
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ec587a6d46
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Merge pull request #172 from lnis-uofu/dev
Basic Support on Multi-Clock Fabric Netlist Generation and Testbench Generation
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2021-01-13 17:14:56 -07:00 |
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Ashton Snelgrove
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afa55f1942
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Merge remote-tracking branch 'origin/master' into github-action-optimizations
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2021-01-13 17:07:54 -07:00 |
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Ashton Snelgrove
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2b705ba17a
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Add building a regression test image on master.
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2021-01-13 17:05:55 -07:00 |
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tangxifan
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2b959290e9
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[Test] Deploy multi-clock test to CI
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2021-01-13 15:44:19 -07:00 |
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tangxifan
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9a906e787b
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[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
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2021-01-13 15:43:31 -07:00 |
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tangxifan
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314e458632
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[Test] Update task configuration to use post-yosys .v file in verification
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2021-01-13 15:42:45 -07:00 |
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tangxifan
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c5a2027f36
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[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
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2021-01-13 15:41:48 -07:00 |
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tangxifan
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7af6d7f07d
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[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
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2021-01-13 15:38:44 -07:00 |
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tangxifan
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9cc9e45b4b
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[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
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2021-01-13 15:13:19 -07:00 |
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Ashton Snelgrove
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4efa5b98e8
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Add docker distribution image.
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2021-01-13 13:58:20 -07:00 |
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tangxifan
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91f12071d5
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[Test] Use counter4bit in the multi-clock test
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2021-01-13 13:34:59 -07:00 |
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tangxifan
|
ccf3e037ff
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[Benchmark] Change multi-clock counter from 8-bit to 4-bit
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2021-01-13 13:31:06 -07:00 |
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tangxifan
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250adb01cf
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[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
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2021-01-13 13:18:31 -07:00 |
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tangxifan
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c0da6b900a
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[Tool] Bug fix in creating multi-bit clock port connections
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2021-01-12 18:38:00 -07:00 |
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tangxifan
|
99e2a068fb
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[Test] Add a test case for multi-clock
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2021-01-12 18:06:25 -07:00 |
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tangxifan
|
2f1aceda67
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[Doc] Update documentation about architecture naming rules
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2021-01-12 18:01:24 -07:00 |
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tangxifan
|
9fa49c401c
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[Arch] Add openfpga architecture which uses 4 global clocks
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2021-01-12 18:00:22 -07:00 |
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tangxifan
|
16b4e89326
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[Doc] Update documentation for VPR architectures
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2021-01-12 17:57:40 -07:00 |
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tangxifan
|
7ccdff4543
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[Arch] Add an architecture using 4 clocks
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2021-01-12 17:55:57 -07:00 |
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tangxifan
|
3790f2c26a
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[Benchmark] Add 2-clock micro benchmark
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2021-01-12 17:48:52 -07:00 |
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tangxifan
|
a0b9f2b40d
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Merge pull request #170 from lnis-uofu/dev
Extended Support on Defining Global Ports from Physical Tile Ports
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2021-01-11 10:02:31 -07:00 |
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tangxifan
|
30aaab0c2e
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[Test] Deploy new test to CI
|
2021-01-10 11:53:49 -07:00 |
|
tangxifan
|
65b2fe3ab7
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[Tool] Bug fix in the global tile connection by considering all the subtiles
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2021-01-10 11:52:38 -07:00 |