Commit Graph

3074 Commits

Author SHA1 Message Date
Laboratory for Nano Integrated Systems (LNIS) 16128f0905
Merge pull request #107 from LNIS-Projects/dev
Enable Customized Fabric Netlist Location in Verilog Testbench Generation
2020-10-12 13:47:40 -06:00
tangxifan 6b6c018945 [Test] Add the new test case to CI 2020-10-12 12:54:51 -06:00
tangxifan dc68c52d0a [Test] Now use a light architecture to speed up the test case runtime 2020-10-12 12:53:34 -06:00
tangxifan e59377a3ec [Flow] bug fix in the sample script for fabric netlist customization 2020-10-12 12:52:01 -06:00
tangxifan 8941e38613 [Test] Enable verification in the new test case 2020-10-12 12:50:08 -06:00
tangxifan 9e1fd300dc [Test] Add test case for customized location of fabric netlists 2020-10-12 12:47:58 -06:00
tangxifan e510e79c12 [Flow] Add openfpga shell example script to use fabric netlist option 2020-10-12 12:42:43 -06:00
tangxifan 3aeea724de [Documentation] Update for new options in fpga-verilog 2020-10-12 12:36:24 -06:00
tangxifan 1ef0898f41 [Tool] Now users can specify a different fabric netlist when generating Verilog testbench 2020-10-12 12:31:51 -06:00
Laboratory for Nano Integrated Systems (LNIS) 5efe1ae77d
Merge pull request #106 from LNIS-Projects/dev
Documentation update
2020-10-10 23:16:37 -06:00
tangxifan ccaa697e5a [Documentation] Add links to technical features to examples 2020-10-10 22:40:37 -06:00
tangxifan ea3a1b785c [Documentation] Fix the path to OpenFPGA logo in the README 2020-10-10 21:44:18 -06:00
Laboratory for Nano Integrated Systems (LNIS) 8493345b52
Merge pull request #105 from LNIS-Projects/dev
Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates
2020-10-10 21:43:02 -06:00
tangxifan b8c20959b6 [Regression test] Add new test case to CI 2020-10-10 20:29:00 -06:00
tangxifan 82e7b159ce [Regression test] Add test case for fracturable LUT using AND gate to switch modes 2020-10-10 20:26:41 -06:00
tangxifan d0014878d5 [Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes 2020-10-10 20:24:57 -06:00
tangxifan 721bcce373 [Tool] Change analysis SDC file name to track netlist name 2020-10-10 17:43:35 -06:00
tangxifan 5fece94e7c
Merge pull request #103 from lukefahr/doc_fix
Docs:  Updated note to enable VPR's GUI
2020-10-08 15:56:44 -06:00
tangxifan 521accdc88
Merge pull request #104 from lukefahr/disp_fix
FLOW:  fixed display flag
2020-10-07 09:54:06 -06:00
tangxifan 7b12c28e4f
Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
2020-10-06 20:05:02 -06:00
Andrew Lukefahr 33bbe0ec48 FLOW: fixed display flag 2020-10-06 20:52:28 -04:00
Andrew Lukefahr 00295a003f Docs: Updated note to enable VPR's GUI 2020-10-06 20:47:43 -04:00
Andrew Lukefahr d68427e47b Fixed blif formatting bug 2020-10-06 20:46:50 -04:00
Laboratory for Nano Integrated Systems (LNIS) 5464d9f2c4
Merge pull request #101 from LNIS-Projects/dev
Documentation Update to Include Technical Features
2020-10-06 13:55:10 -06:00
tangxifan 800931c840 [Documentation] Add configuration protocol to technical highlights 2020-10-06 12:16:15 -06:00
tangxifan 56ab63d939 [Documentation] Fix format in table 2020-10-06 12:02:15 -06:00
tangxifan c8339fc473 [Documentation] Typo fix 2020-10-06 12:00:30 -06:00
tangxifan 113708c68f [Documentation] Reorganization the overview part by adding technical highlights 2020-10-06 11:56:10 -06:00
tangxifan 02e21d115b [Documentation] Update 3-rd party tool version requirements 2020-10-06 10:00:12 -06:00
tangxifan 7d5dbab304
Merge pull request #100 from lukefahr/bug_fixes
Edits to enable basic run_fpga_flow.py
2020-10-02 10:14:30 -06:00
Andrew Lukefahr 2d92a1f1af Edits to enable basic run_fpga_flow.py 2020-10-02 10:18:10 -04:00
Laboratory for Nano Integrated Systems (LNIS) 7a139c91a1
Merge pull request #98 from LNIS-Projects/dev
Support of multiple regions for configuration chain
2020-09-29 17:34:43 -06:00
tangxifan 67300af987 [Documentation] Update motivation with new set of figures 2020-09-29 16:52:16 -06:00
tangxifan 6817c045c2 [Documentation] Update tutorial about tooling 2020-09-29 16:24:52 -06:00
tangxifan 639d57016b [Documentation] Update documentation about the multi-region configuration 2020-09-29 15:55:42 -06:00
tangxifan d4d02ab16a [Regression Test] Move fabric key tests to basic tests 2020-09-29 14:22:23 -06:00
tangxifan ff6570df9d [Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI 2020-09-29 14:19:40 -06:00
tangxifan 4f00d310d3 [Architecture] Add example fabric key using multiple regions 2020-09-29 14:14:50 -06:00
tangxifan 02ea639959 [Regression Test] Add test for fabric key based on multiple region 2020-09-29 14:13:38 -06:00
tangxifan 462886fb5f [Documentation] Update documentation for the multiple region support on configuration chain 2020-09-29 14:02:03 -06:00
tangxifan 6e8ebd7979 [Regression Tests] Deploy multi-region test cases to CI 2020-09-29 13:57:31 -06:00
tangxifan a0d1d68402 [Regression Test] Add regression tests for smart fast configuration chain using multiple regions 2020-09-29 13:53:41 -06:00
tangxifan d5c7411399 [Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain 2020-09-29 13:50:31 -06:00
tangxifan 5be5835b71 [Regression Test] Add multiple region configuration chain test case 2020-09-29 13:48:39 -06:00
tangxifan 23449dc5c3 [Architecture] Add multiple region configuration chain architecture 2020-09-29 13:46:40 -06:00
tangxifan e0d7bcfa11 [Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols 2020-09-29 12:49:32 -06:00
tangxifan e988e35f81 [Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches 2020-09-29 12:22:10 -06:00
tangxifan 180d72f3e5 [Tool] Add regions to fabric bitstream 2020-09-28 21:04:08 -06:00
tangxifan e179a58b15 [OpenFPGA Tool] Bug fix for long runtime 2020-09-28 20:42:18 -06:00
tangxifan 47f3c79927 [OpenFPGA Tool] Bug fix in module manager due to configurable regions 2020-09-28 19:08:19 -06:00