3 Commits

Author	SHA1	Message	Date
tangxifan	89f9d24d32	[Flow] Update simulation settings for multiple clock to allow unique clock port name	2021-01-15 10:35:43 -07:00
tangxifan	dbed04b53b	[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI	2021-01-14 15:42:21 -07:00
tangxifan	923f3a3401	[Flow] Add an example simulation settings for a 4-clock FPGA fabric	2021-01-13 17:29:39 -07:00