tangxifan
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38601f325b
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[Engine] Add bus group to OpenFPGA core
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2022-02-17 17:28:55 -08:00 |
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tangxifan
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0670c2de59
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[Tool] Deploy pin constraints to preconfig Verilog module generation
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2021-01-19 16:56:30 -07:00 |
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tangxifan
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ad7a54db1b
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[Tool] Add repack dc library to compilation
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2021-01-16 17:20:59 -07:00 |
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tangxifan
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4f8260a7ba
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remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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tangxifan
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675a59ecb8
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Move fpga_bitstream to the libopenfpga library and add XML reader
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2020-06-20 18:25:17 -06:00 |
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tangxifan
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3499b4d3e7
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add fabric key writer for top-level module
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2020-06-12 10:41:34 -06:00 |
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tangxifan
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65c81e14b2
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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tangxifan
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523f9ac391
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start implement openfpga shell and use vpr as a macro
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2020-01-22 20:20:10 -07:00 |