tangxifan
|
d2a68ff9c5
|
[core] now corner tile are considered as config child
|
2024-07-04 13:25:57 -07:00 |
|
tangxifan
|
75407b1e8c
|
[lib] update vtr
|
2024-07-04 13:15:54 -07:00 |
|
tangxifan
|
b80ed8d15c
|
[core] fixed a bug
|
2024-07-04 12:58:16 -07:00 |
|
tangxifan
|
a3723b33b3
|
[core] fixed a minor bug
|
2024-07-04 12:52:29 -07:00 |
|
tangxifan
|
a717882304
|
[core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks
|
2024-07-04 12:44:48 -07:00 |
|
tangxifan
|
48590df452
|
[lib] update vtr
|
2024-07-04 12:20:20 -07:00 |
|
tangxifan
|
5736f45f76
|
[lib] update vtr
|
2024-07-04 12:18:20 -07:00 |
|
tangxifan
|
93649a1244
|
[lib] update vtr
|
2024-07-04 12:16:32 -07:00 |
|
tangxifan
|
724c14d1f7
|
[core] fixed a bug on build top module connections on perimeter gsb when cbs occur
|
2024-07-04 11:09:01 -07:00 |
|
tangxifan
|
550ce0c390
|
[core] fixed the bug on build gsb when cbs are on perimeters
|
2024-07-04 10:58:44 -07:00 |
|
tangxifan
|
e06b53658c
|
[lib] update vtr
|
2024-07-03 22:33:48 -07:00 |
|
tangxifan
|
bc94e08c77
|
[lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled
|
2024-07-03 22:28:22 -07:00 |
|
tangxifan
|
3d19e10611
|
[lib] update vtr
|
2024-07-03 21:48:37 -07:00 |
|
tangxifan
|
a78fddc3cb
|
[test] add a new testcase to validate perimeter cb
|
2024-07-03 19:59:24 -07:00 |
|
tangxifan
|
a27325d987
|
[core] code format
|
2024-07-03 17:05:27 -07:00 |
|
tangxifan
|
f681c6a903
|
[core] update API call due to vtr upgrade
|
2024-07-03 17:04:06 -07:00 |
|
tangxifan
|
60f0c087d8
|
[lib] update vtr to latest
|
2024-07-03 16:54:34 -07:00 |
|
tangxifan
|
27d23399b5
|
Merge pull request #1737 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-02 21:11:32 -07:00 |
github-actions[bot]
|
50e87232ed
|
Updated Patch Count
|
2024-07-03 04:10:48 +00:00 |
|
tangxifan
|
0426d47026
|
Merge pull request #1736 from lnis-uofu/xt_clkntwk2
[doc] typo
|
2024-07-02 21:10:26 -07:00 |
|
tangxifan
|
abef0e3478
|
Merge branch 'master' into xt_clkntwk2
|
2024-07-02 20:12:38 -07:00 |
|
tangxifan
|
e3a258a5ab
|
[doc] typo
|
2024-07-02 19:31:45 -07:00 |
|
tangxifan
|
37c640faef
|
Merge pull request #1735 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-02 18:09:12 -07:00 |
|
github-actions[bot]
|
6d30871f11
|
Updated Patch Count
|
2024-07-03 00:15:44 +00:00 |
|
tangxifan
|
5531d416cc
|
Merge pull request #1734 from lnis-uofu/xt_clkntwk2
Programmable Clock Network v2.0
|
2024-07-02 17:15:23 -07:00 |
|
tangxifan
|
078fad1e74
|
[test] typo
|
2024-07-02 14:57:24 -07:00 |
|
tangxifan
|
7e461b09f8
|
[core] add missing file
|
2024-07-02 13:22:41 -07:00 |
|
tangxifan
|
1e7cca8ceb
|
[arch] code format
|
2024-07-02 11:52:30 -07:00 |
|
tangxifan
|
29452a7442
|
[test] fixed a bug on out-of-date arch
|
2024-07-02 11:52:19 -07:00 |
|
tangxifan
|
9b5df76fd5
|
[test] fix a bug in arch
|
2024-07-02 09:33:16 -07:00 |
|
tangxifan
|
1dfbef5a54
|
Merge branch 'master' into xt_clkntwk2
|
2024-07-01 21:42:30 -07:00 |
|
tangxifan
|
ec7ca1add1
|
[doc] add example to example clock network
|
2024-07-01 21:41:33 -07:00 |
|
tangxifan
|
578d7c8ec0
|
[core] fixed a bug on region tap point identification
|
2024-07-01 20:58:41 -07:00 |
|
tangxifan
|
73b30841a7
|
[lib] typo
|
2024-07-01 20:56:27 -07:00 |
|
tangxifan
|
60e6e27e54
|
[core] fixed a bug on tap point identificatin
|
2024-07-01 20:45:55 -07:00 |
|
tangxifan
|
e00312d29e
|
[test] typo
|
2024-07-01 20:34:37 -07:00 |
|
tangxifan
|
1bfcf7574c
|
[test] validate region and single syntax
|
2024-07-01 20:33:28 -07:00 |
|
tangxifan
|
a85a6f1674
|
[core] code format
|
2024-07-01 17:57:10 -07:00 |
|
tangxifan
|
70428fd969
|
[lib] add sanity checks on global port name and clock network's global port name
|
2024-07-01 17:56:29 -07:00 |
|
tangxifan
|
df23daf026
|
[lib] sanity check on global port name and from pin name of tap points
|
2024-07-01 17:37:16 -07:00 |
|
tangxifan
|
7c487eadc9
|
[core] now clock network keep port info in a native data structure
|
2024-07-01 16:58:23 -07:00 |
|
tangxifan
|
58a70ad581
|
Merge pull request #1733 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-01 16:44:00 -07:00 |
|
github-actions[bot]
|
24e2829899
|
Updated Patch Count
|
2024-07-01 23:26:27 +00:00 |
|
tangxifan
|
69792d807f
|
Merge pull request #1732 from lnis-uofu/dependabot/submodules/yosys-a739e21
Bump yosys from `07daf61` to `a739e21`
|
2024-07-01 16:26:10 -07:00 |
dependabot[bot]
|
e007094112
|
Bump yosys from `07daf61` to `a739e21`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `07daf61` to `a739e21`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](07daf61ae6...a739e21a5f)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-01 06:06:57 +00:00 |
|
tangxifan
|
18e2b994ac
|
[doc] update syntax on clock network file
|
2024-06-30 22:56:31 -07:00 |
|
tangxifan
|
3afb92d6a5
|
[core] code format
|
2024-06-30 22:48:15 -07:00 |
|
tangxifan
|
28e3cb799e
|
[test] update 2-clock arch and pcf
|
2024-06-29 17:40:20 -07:00 |
|
tangxifan
|
12c9686c27
|
[test] fixed some bugs on arch
|
2024-06-29 17:38:34 -07:00 |
|
tangxifan
|
1fd974d544
|
[core] fixed a bug where clock network size cannot impact global port on top module
|
2024-06-29 17:35:47 -07:00 |