tangxifan
|
977283dd34
|
[core] typo
|
2024-07-10 14:12:49 -07:00 |
|
tangxifan
|
af996e563e
|
[test] add a new test to validate reset generated by internal driver through programmable clock network
|
2024-07-10 14:11:06 -07:00 |
|
tangxifan
|
213914e4ac
|
[core] code format
|
2024-07-10 12:23:57 -07:00 |
|
tangxifan
|
48e159dd8d
|
[core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches
|
2024-07-10 12:23:15 -07:00 |
|
tangxifan
|
c6dd33a965
|
[core] fixed a bug when annotating global nets on OPIN
|
2024-07-10 11:59:25 -07:00 |
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tangxifan
|
b6ff69faac
|
[test] reworking the testcase to validate clock network with internal drivers
|
2024-07-10 11:36:22 -07:00 |
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tangxifan
|
dbe8e63f53
|
[test] remove unused files
|
2024-07-10 10:15:47 -07:00 |
|
tangxifan
|
77304164f4
|
[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
|
2024-07-10 10:13:41 -07:00 |
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tangxifan
|
191a3d1c5e
|
[test] update W
|
2024-07-10 10:01:31 -07:00 |
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tangxifan
|
81fe722d98
|
[test] adjust W
|
2024-07-09 23:49:01 -07:00 |
dependabot[bot]
|
66a77c8658
|
Bump yosys from `dac5bd1` to `b08688f`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `dac5bd1` to `b08688f`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](dac5bd1983...b08688f711)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-10 06:25:00 +00:00 |
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tangxifan
|
96bdcc8b35
|
[core] code format
|
2024-07-09 22:54:55 -07:00 |
|
tangxifan
|
63f2a07c86
|
[test] typo
|
2024-07-09 22:54:33 -07:00 |
|
tangxifan
|
27e29f949c
|
[core] fixed a bug where the pin idx of global net on rr graph is not well annotated
|
2024-07-09 22:53:12 -07:00 |
|
tangxifan
|
a16b3df063
|
[test] update arch to allow clock access on CLB inputs
|
2024-07-09 20:59:44 -07:00 |
|
tangxifan
|
0f78803759
|
[core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs
|
2024-07-09 20:47:15 -07:00 |
|
tangxifan
|
43dbeafd44
|
[test] typo
|
2024-07-09 20:27:28 -07:00 |
|
tangxifan
|
9ce4b57363
|
[test] typo
|
2024-07-09 20:25:39 -07:00 |
|
tangxifan
|
e5d146a67a
|
[test] add new tests to validate rst on lut and clk on lut features
|
2024-07-09 20:24:23 -07:00 |
|
tangxifan
|
89e6a0483f
|
[test] add a new benchmark to validate rst and clk on LUTs
|
2024-07-09 18:45:33 -07:00 |
|
tangxifan
|
38bb5aa906
|
[test] add a new benchmark to validate clock on LUT
|
2024-07-09 18:42:39 -07:00 |
|
tangxifan
|
a155ea4b41
|
Merge pull request #1743 from lnis-uofu/dependabot/submodules/yosys-dac5bd1
Bump yosys from `a739e21` to `dac5bd1`
|
2024-07-09 16:15:21 -07:00 |
|
tangxifan
|
e3caff56ee
|
Merge pull request #1745 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-09 16:14:57 -07:00 |
github-actions[bot]
|
f0e168c2b3
|
Updated Patch Count
|
2024-07-09 21:54:39 +00:00 |
|
tangxifan
|
a2afdae0cc
|
Merge pull request #1741 from lnis-uofu/xt_clkntwk2
Support Connection Blocks on Perimeter Tiles
|
2024-07-09 14:54:16 -07:00 |
|
tangxifan
|
f42884304a
|
[doc] update clock network details
|
2024-07-09 11:40:41 -07:00 |
|
tangxifan
|
5efc9d0e00
|
[test] update golden outputs
|
2024-07-08 23:24:16 -07:00 |
|
tangxifan
|
092b8b038f
|
[core] remove verbose out
|
2024-07-08 22:23:37 -07:00 |
|
tangxifan
|
04504e4d5d
|
[core] code format
|
2024-07-08 22:22:59 -07:00 |
|
tangxifan
|
1cdb1c5995
|
[core] fixed a bug on calculating subtile pins
|
2024-07-08 22:22:08 -07:00 |
|
tangxifan
|
5cb104a5f6
|
[test] fixed a bug
|
2024-07-08 22:04:40 -07:00 |
|
tangxifan
|
bf484dbc70
|
[doc] add perimeter cb examples on prog clk network
|
2024-07-08 21:25:12 -07:00 |
|
tangxifan
|
229adebe07
|
[doc] new option to write_fabric_verilog
|
2024-07-08 21:06:12 -07:00 |
|
tangxifan
|
41839bfd7a
|
[test] typo
|
2024-07-08 20:21:40 -07:00 |
|
tangxifan
|
8a5c33b1d6
|
[doc] new option for perimeter cb
|
2024-07-08 19:01:16 -07:00 |
|
tangxifan
|
03c1c6f917
|
[test] code format
|
2024-07-08 18:35:23 -07:00 |
|
tangxifan
|
c7d6c3ab61
|
[arch] now all the outputs of I/O can only on 1 side
|
2024-07-08 18:34:13 -07:00 |
|
tangxifan
|
ad053cddca
|
[test] code format
|
2024-07-08 18:02:30 -07:00 |
|
tangxifan
|
fe06c2f2b1
|
[core] code format
|
2024-07-08 16:18:58 -07:00 |
|
tangxifan
|
db459b0e87
|
[core] add verbose outputs
|
2024-07-08 16:18:32 -07:00 |
|
tangxifan
|
e8f9deeeaf
|
[core] fixed a critical bug on computing pin index for subtile in clock taps
|
2024-07-08 16:12:20 -07:00 |
|
tangxifan
|
6dde383a7f
|
[core] debugging
|
2024-07-08 16:00:18 -07:00 |
|
tangxifan
|
c30eafac9f
|
[test] fixed a bug on clk ntwk arch where some io clocks are not tapped
|
2024-07-08 15:26:16 -07:00 |
|
tangxifan
|
8bca3d79be
|
[core] fixed a bug where tap points of clock network cannot reach perimeter cb
|
2024-07-08 15:17:24 -07:00 |
|
tangxifan
|
b50acacfba
|
[test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles
|
2024-07-08 15:09:31 -07:00 |
|
tangxifan
|
549dc6e7e6
|
[lib] update vtr
|
2024-07-08 13:39:55 -07:00 |
|
tangxifan
|
ab454be831
|
[lib] update vtr
|
2024-07-08 13:32:54 -07:00 |
|
tangxifan
|
7bd60f5f7d
|
[core] support perimeter cb when identify pins of I/Os tiles
|
2024-07-08 12:39:54 -07:00 |
|
tangxifan
|
6492d43a01
|
[test] add a new test to validate perimeter cb using global tile clock
|
2024-07-08 11:29:20 -07:00 |
|
tangxifan
|
48ae3691c4
|
[test] typo
|
2024-07-08 10:57:54 -07:00 |