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OpenFPGA
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419 Commits 70 Branches 8 Tags 105 MiB
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4 Commits

Author SHA1 Message Date
tangxifan 17bc7fc296 update Verilog generator to use GSB data structure. SDC generator and TCL generator to go 2019-06-08 20:11:22 -06:00
tangxifan 2c46da6888 clean-up warnings Verilog routing generator 2019-05-24 16:29:17 -06:00
tangxifan be4643b8a6 updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated 2019-05-10 10:21:06 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00