tangxifan
|
8fc258cc93
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-25 15:33:37 -06:00 |
|
tangxifan
|
c43fabb43c
|
developed verilog instance writer. refactoring on mux ongoing
|
2019-08-25 10:31:45 -06:00 |
|
tangxifan
|
fe7dfd59c3
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-24 23:54:37 -06:00 |
|
tangxifan
|
63f40f48fa
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-24 19:23:33 -06:00 |
|
tangxifan
|
27b619554d
|
add stats for verilog modules
|
2019-08-23 20:23:42 -06:00 |
|
tangxifan
|
ad06e9c98c
|
plug in module manager
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
39853408dd
|
add recursive global port searching for circuit library
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
fcb31e4c24
|
add stats for verilog modules
|
2019-08-23 18:41:16 -06:00 |
|
tangxifan
|
8eebca9daa
|
plug in module manager
|
2019-08-23 17:39:29 -06:00 |
|
tangxifan
|
37a092e885
|
add recursive global port searching for circuit library
|
2019-08-23 16:36:30 -06:00 |
|
tangxifan
|
931b042750
|
refactoring module manager
|
2019-08-23 12:52:01 -06:00 |
|
tangxifan
|
732e24767f
|
developing module manager
|
2019-08-22 23:49:35 -06:00 |
|
tangxifan
|
3f45e6cc87
|
remove dead codes for essential gates code generation
|
2019-08-22 10:01:52 -06:00 |
|
tangxifan
|
43de2d7636
|
some tuning on Verilog port formatting
|
2019-08-21 23:47:50 -06:00 |
|
tangxifan
|
1be5632e92
|
minor tuning on the delay assignment
|
2019-08-21 23:11:54 -06:00 |
|
tangxifan
|
7b0c55ce15
|
try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
|
2019-08-21 22:45:48 -06:00 |
|
tangxifan
|
5a40c6713d
|
managed to plug in refactored essential gates, dead codes to be removed
|
2019-08-21 21:50:26 -06:00 |
|
tangxifan
|
d8eb9866a0
|
refactored gate verilog generation
|
2019-08-21 18:49:48 -06:00 |
|
tangxifan
|
b08ff465c9
|
refactored pass-gate verilog generation
|
2019-08-21 17:33:16 -06:00 |
|
tangxifan
|
5e156dc725
|
minor fix for OSX and update travis using ccache to speed up compilation
|
2019-08-21 15:25:36 -06:00 |
|
tangxifan
|
9c43b1b753
|
complete refacotriing the inv and buf part in submodules
|
2019-08-21 14:54:05 -06:00 |
|
tangxifan
|
a40e5c91ca
|
refactored power-gate inverter
|
2019-08-20 21:56:55 -06:00 |
|
tangxifan
|
19472ace4e
|
renaming files
|
2019-08-20 21:01:38 -06:00 |
|
tangxifan
|
59f1ac7310
|
add missing files and try to refactor submodule essential
|
2019-08-20 20:49:26 -06:00 |
|
tangxifan
|
5f55fc7b49
|
add missing files and developing essential gates
|
2019-08-20 20:43:46 -06:00 |
|
tangxifan
|
60e8d2b29f
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
tangxifan
|
29104b6fa5
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
a7ac1e4980
|
remame methods in circuit_library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
69039aa742
|
developed subgraph extraction and start refactoring mux generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
bee070d7cc
|
start plug in MUX library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
893683fa95
|
start developing mux library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
153d506abb
|
add graph-based mux decoding function
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
dcca9f4f0f
|
finish mux graph builders
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
638969c3c9
|
adding mux graph data structures
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
0b8473e960
|
start developing graphs for muxes, with aims to simplify netlist and bitstream generation
|
2019-08-20 15:24:52 -06:00 |
Ganesh Gore
|
69ffc38645
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-19 21:59:06 -06:00 |
|
Ganesh Gore
|
7bfc48b8e4
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
tangxifan
|
aa7f3bef7f
|
fixed bugs in configure pb_rr_graph and dependence on testbenches
|
2019-08-16 18:20:30 -06:00 |
|
tangxifan
|
e456b6f905
|
replace spice_models with circuit model in bitstream generator
|
2019-08-16 16:36:49 -06:00 |
|
tangxifan
|
5ece7ab6d0
|
start refactoring the bitstream part using spice_models
|
2019-08-16 15:58:14 -06:00 |
|
tangxifan
|
b66e120366
|
patch on local encoders for unused configuration, avoid chip-burn issues
|
2019-08-16 15:32:23 -06:00 |
|
tangxifan
|
4eb046760b
|
still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
|
2019-08-15 21:57:59 -06:00 |
AurelienUoU
|
8e38aa6019
|
Merge with heterogeneous for unfracturable LUT bug fix
|
2019-08-14 10:10:27 -06:00 |
|
AurelienUoU
|
df873903f8
|
Bug fix for non fracturable LUT
|
2019-08-14 09:32:15 -06:00 |
|
AurelienUoU
|
30c0f2b6b7
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-14 09:11:54 -06:00 |
|
AurelienUoU
|
90aaed6e1f
|
Fix regression test
|
2019-08-14 09:10:13 -06:00 |
|
tangxifan
|
d2d8af5416
|
bug fixing for pb_type num_conf_bits and num_iopads stats
|
2019-08-13 17:34:09 -06:00 |
|
tangxifan
|
edfa72a666
|
try to fix the bug in clock net identification
|
2019-08-13 16:47:28 -06:00 |
|
tangxifan
|
1118b28397
|
use single subckt for switch box again, to abolish the multi-module subckt
|
2019-08-13 16:11:04 -06:00 |
|
tangxifan
|
4cffd8ac2d
|
keep route file updated with tileable rr_graph
|
2019-08-13 15:37:42 -06:00 |
|
tangxifan
|
c7526cb43c
|
memory sanitized
|
2019-08-13 14:19:40 -06:00 |
|
tangxifan
|
ef4d15df4e
|
reorganize the libarchfpga repository
|
2019-08-13 13:37:35 -06:00 |
|
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
|
AurelienUoU
|
8dab4dec90
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-13 11:09:29 -06:00 |
|
AurelienUoU
|
7851246424
|
Resolve merge issue
|
2019-08-13 11:08:30 -06:00 |
|
tangxifan
|
c56f289d3e
|
add checkers for circuit library
|
2019-08-12 16:45:33 -06:00 |
|
tangxifan
|
d4ae160d3a
|
start adding circuit library checkers
|
2019-08-12 14:20:11 -06:00 |
|
AurelienUoU
|
2da4d3f33c
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-08-12 09:57:02 -06:00 |
|
tangxifan
|
fbdab32a2d
|
timing graph for circuit models are working
|
2019-08-10 13:03:24 -06:00 |
|
tangxifan
|
c004699a14
|
complete parsers for ports
|
2019-08-09 21:00:41 -06:00 |
|
tangxifan
|
2c7d6e3de4
|
adding port parsers
|
2019-08-09 17:48:55 -06:00 |
|
tangxifan
|
f80e58c753
|
developing a in-house tokenizer
|
2019-08-09 16:36:22 -06:00 |
|
tangxifan
|
3d7adb3dd9
|
start developing parsers for delay values
|
2019-08-09 15:52:28 -06:00 |
|
tangxifan
|
6b5ac2e1ef
|
add timing graph builder for circuit models
|
2019-08-09 12:45:03 -06:00 |
|
tangxifan
|
c8d04c4f00
|
plug in fast look-up builder
|
2019-08-08 21:20:28 -06:00 |
|
tangxifan
|
158c67075e
|
built a conversion from spice_models to circuit_library and plug in
|
2019-08-08 17:25:27 -06:00 |
|
tangxifan
|
e19485bbb7
|
add more accessors and more to be added when plug into framework
|
2019-08-08 14:16:29 -06:00 |
|
tangxifan
|
ad8c33e1ba
|
complete the mutators
|
2019-08-08 11:33:11 -06:00 |
|
tangxifan
|
5b0c9572c3
|
add mutators for delay_info
|
2019-08-07 21:19:16 -06:00 |
|
tangxifan
|
03a64e2ad8
|
complete the mutators for ports
|
2019-08-07 20:54:27 -06:00 |
|
tangxifan
|
9f8c7a3fc7
|
adding port mutators
|
2019-08-07 17:47:39 -06:00 |
|
tangxifan
|
ed4642a23f
|
adding basic mutators
|
2019-08-07 17:12:05 -06:00 |
|
tangxifan
|
38962c4607
|
adding member functions for circuit library
|
2019-08-07 15:45:27 -06:00 |
|
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |
|
tangxifan
|
f57495feba
|
Now we can also auto-generate the Verilog for a mux2 std cell
|
2019-08-06 15:19:01 -06:00 |
|
tangxifan
|
afa468a442
|
hotfix in minor Verilog generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
b4f3dfc82d
|
bug fixing for local encoder's bitstream generation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
3a490fdd59
|
bug fixing on the port map alignment
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
c08c136844
|
set a working range for the encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
557b1af633
|
add Verilog generation for local encoders, bitstream upgrade TODO
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
33f3a991b5
|
init effort to start developing mux local encoders
|
2019-08-06 14:17:55 -06:00 |
|
AurelienUoU
|
40b7f1cc53
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-07-29 11:45:23 -06:00 |
|
tangxifan
|
32e3a556b9
|
bug fixing herited from explicit mapping
|
2019-07-17 09:26:05 -06:00 |
|
tangxifan
|
8b8e18a8de
|
bug fixing for mux subckt names
|
2019-07-17 08:59:57 -06:00 |
|
tangxifan
|
a2505ff16a
|
turn on std cell explicit port map
|
2019-07-17 08:36:09 -06:00 |
|
tangxifan
|
dcc96bf7f5
|
bug fixing
|
2019-07-17 08:25:52 -06:00 |
|
tangxifan
|
6e1d49d74e
|
start to support direct mapping to MUX2 standard cells
|
2019-07-17 07:54:23 -06:00 |
|
tangxifan
|
e9154b1f74
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 14:42:45 -06:00 |
|
tangxifan
|
115411941b
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 13:15:45 -06:00 |
Baudouin Chauviere
|
69014704ef
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
|
Baudouin Chauviere
|
e602006a07
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
|
2019-07-16 12:45:13 -06:00 |
|
AurelienUoU
|
b810b5cab9
|
fpga_flow bug fix + upload k8 architecture
|
2019-07-16 07:04:45 -06:00 |
|
AurelienUoU
|
35e1962732
|
Merge branch 'dev' into documentation
|
2019-07-15 21:19:26 -06:00 |
|
AurelienUoU
|
1cf4e78502
|
Update documentation and help
|
2019-07-15 21:16:15 -06:00 |
|
tangxifan
|
bcc6346533
|
speeding up identifying unique modules in routing
|
2019-07-14 13:49:20 -06:00 |
|
tangxifan
|
4c6e245885
|
speed-up the unique routing process
|
2019-07-14 12:22:00 -06:00 |