tangxifan
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3b2a4c5387
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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tangxifan
|
57a24570f5
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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tangxifan
|
3f91b8433e
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[Tool] Change the i/o numbering to the clockwise sequence
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2020-11-13 15:00:25 -07:00 |
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tangxifan
|
088198c861
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[Tool] enhance error checking in fabric key parser
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2020-11-13 10:56:00 -07:00 |
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tangxifan
|
372fb261fd
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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tangxifan
|
e627b6dd5d
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[Tool] Enhance port attribute checks in tile annotation data structure
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2020-11-11 13:41:05 -07:00 |
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tangxifan
|
9cbc374b33
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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tangxifan
|
81e56d45d6
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[Tool] Update FPGA-SDC to use the new data structure for global ports
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2020-11-10 21:17:17 -07:00 |
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tangxifan
|
c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
|
dcb50e4f19
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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tangxifan
|
cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
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2020-11-10 16:59:00 -07:00 |
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tangxifan
|
5fe9c27600
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[Tool] Remove redundant assertation
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2020-11-09 09:42:39 -07:00 |
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tangxifan
|
ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
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tangxifan
|
9b0617ffe6
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[Tool] Bug fix for mappable I/O support
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2020-11-04 20:45:51 -07:00 |
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tangxifan
|
37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
|
4a2874b2bc
|
[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
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tangxifan
|
1e47203c7c
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[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
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2020-11-02 18:35:26 -07:00 |
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tangxifan
|
e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
|
1fd899ecee
|
[Tool] Relex logic block checking codes to skip zero-capacity nodes
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2020-11-02 16:57:19 -07:00 |
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tangxifan
|
6b25cf720d
|
[Tool] Comment on the memory efficiency on fabric bitstream address storage
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2020-10-30 22:09:48 -06:00 |
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tangxifan
|
b78f8bec16
|
[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
|
5bcd559851
|
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
|
0d77916041
|
[Tool] Support multi-region frame-based configuration protocol
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2020-10-30 10:43:11 -06:00 |
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tangxifan
|
8ef6ae32fb
|
[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
|
2020-10-29 17:35:55 -06:00 |
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tangxifan
|
987eccf586
|
[Tool] Bug fix in multi-region memory bank; Basic test passed
|
2020-10-29 16:26:45 -06:00 |
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tangxifan
|
448e88645a
|
[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
|
bd49ea95d4
|
[Tool] Add function to comput configuration bits by region
|
2020-10-28 12:37:09 -06:00 |
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tangxifan
|
446f982410
|
[Tool] Add warning when number of regions defined in fabric key is different than architecture
|
2020-10-28 11:43:05 -06:00 |
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tangxifan
|
1ef0898f41
|
[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
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tangxifan
|
721bcce373
|
[Tool] Change analysis SDC file name to track netlist name
|
2020-10-10 17:43:35 -06:00 |
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tangxifan
|
e0d7bcfa11
|
[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
|
2020-09-29 12:49:32 -06:00 |
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tangxifan
|
e988e35f81
|
[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
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2020-09-29 12:22:10 -06:00 |
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tangxifan
|
180d72f3e5
|
[Tool] Add regions to fabric bitstream
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2020-09-28 21:04:08 -06:00 |
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tangxifan
|
e179a58b15
|
[OpenFPGA Tool] Bug fix for long runtime
|
2020-09-28 20:42:18 -06:00 |
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tangxifan
|
47f3c79927
|
[OpenFPGA Tool] Bug fix in module manager due to configurable regions
|
2020-09-28 19:08:19 -06:00 |
|
tangxifan
|
f93d46a870
|
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
|
2020-09-28 19:03:19 -06:00 |
|
tangxifan
|
552dddffd0
|
[OpenFPGA Tool] Support configurable regions in module manager
|
2020-09-28 18:13:07 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |
|
tangxifan
|
154f23b108
|
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
|
2020-09-26 11:54:06 -06:00 |
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tangxifan
|
1b4e449179
|
[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
|
2020-09-25 21:05:20 -06:00 |
|
tangxifan
|
6bea712db0
|
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
|
2020-09-25 14:54:51 -06:00 |
|
tangxifan
|
8468f25b23
|
[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
|
2020-09-24 16:31:55 -06:00 |
|
tangxifan
|
46b12611a9
|
[OpenFPGA Tool] Bug fix for smart fast configuration
|
2020-09-23 22:04:07 -06:00 |
|
tangxifan
|
154c9045f6
|
[OpoenFPGA Tool] Bug fix for smart fast configuration
|
2020-09-23 21:38:42 -06:00 |
|
tangxifan
|
c2c37d7555
|
[OpenFPGA Tool] Add more print-out for smart fast configuration
|
2020-09-23 21:34:23 -06:00 |
|
tangxifan
|
a3abf81afe
|
[OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration
|
2020-09-23 21:25:06 -06:00 |
|
tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
|
tangxifan
|
ad881ea4dc
|
[OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank
|
2020-09-23 18:59:25 -06:00 |
|
tangxifan
|
9adeb550dc
|
[OpenFPGA Tool] Bug fix in fabric builder
|
2020-09-23 18:28:00 -06:00 |
|
tangxifan
|
6480b06a2d
|
[OpenFPGA tool] Remove out-of-data test blif, architecture and scripts
|
2020-09-23 11:01:53 -06:00 |