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OpenFPGA
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Aram Kostanyan
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
tangxifan
b8ced5377f
[Test] Add a test case for i/o mapping writer
2021-04-27 14:41:15 -06:00