5 Commits

Author	SHA1	Message	Date
tangxifan	decc1dc4b2	debugged global gp input/output port support	2020-04-05 17:39:30 -06:00
tangxifan	80bb2baae5	start verification and bug fixing	2020-02-28 14:29:01 -07:00
tangxifan	ae899f3b11	bug fixed for clock names	2020-02-27 16:51:55 -07:00
tangxifan	9b769cd8e4	bug fix for using renamed i/o names	2020-02-27 16:37:20 -07:00
tangxifan	77529f4957	adapt top Verilog testbench generation	2020-02-26 21:30:21 -07:00