6122863548
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
2021-10-09 20:44:28 -07:00
a1eaacf5a8
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
2021-10-06 12:12:15 -07:00
b98a8ec718
[Test] Added the dedicated test case for fixed shift register clock frequency
2021-10-06 12:09:26 -07:00
b21f212031
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
2021-10-05 11:39:53 -07:00
52569f808e
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
2021-10-05 10:57:33 -07:00
fa1908511d
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
2021-10-04 16:36:20 -07:00
dda147e234
[Flow] Add an example simulation setting file for defining programming shift register clocks
2021-10-01 11:04:23 -07:00
89a97d83bd
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
2021-09-29 16:28:06 -07:00
4400dae108
[Test] Bug fix in the wrong arch name
2021-09-28 11:40:25 -07:00
dae3554fd4
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
2021-09-28 11:27:49 -07:00
655b195d8b
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
2021-09-22 15:56:44 -07:00
b0aaab9c03
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
2021-09-22 11:32:13 -07:00
abfa380333
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
2021-09-22 11:27:09 -07:00
51fc222d61
[Test] Added a new test case for multi-region QL memory bank
2021-09-22 10:01:33 -07:00
1412121541
[Test] Added a new test to validate the fabric key parser for QL memory bank
2021-09-21 16:20:24 -07:00
dc2d1d1c3c
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
2021-09-21 15:42:20 -07:00
60fc3ab36c
[Test] Added a new test case for the WLR memory bank
2021-09-20 11:20:36 -07:00
b82cfdf555
[Test] Add the QL memory bank test to regression test cases
2021-09-09 09:29:21 -07:00
64dcdaec61
[Test] Update all the tasks that use counter benchmark
2021-07-02 17:29:13 -06:00
3cbe266c44
[Test] Bug fix on the test case for multi-mode FF and pin constraints
2021-07-02 15:27:27 -06:00
3aacce2a96
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
2021-07-02 14:04:42 -06:00
edd5be2cae
[CI] Added testcase for benchmark variable
2021-07-02 12:51:34 -06:00
5286f9ba25
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
2021-07-02 11:39:00 -06:00
9eeec05a1f
[Test] Bug fix
2021-06-29 19:55:07 -06:00
f32ffb6d61
[Test] Bug fix
2021-06-29 18:51:28 -06:00
c6089385b0
[Misc] Bug fix
2021-06-29 18:34:41 -06:00
5f5a03f17f
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
2021-06-29 18:28:38 -06:00
2c1692e6dc
[Test] Bug fix
2021-06-29 17:54:25 -06:00
30c2f597f2
[Test] Added two cases to validate testbench generation without self checking
2021-06-29 16:06:15 -06:00
c62666e7c3
[Test] Use proper template for some failing tests
2021-06-09 14:24:34 -06:00
462326aaa5
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
2021-06-07 21:50:00 -06:00
5ecd975ec7
[Test] Bug fix
2021-06-07 19:20:10 -06:00
9556f994b4
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
2021-06-07 17:49:40 -06:00
a67196178e
[Test] Now use 'write_full_testbench' in configuration frame test cases
2021-06-07 13:58:15 -06:00
27fa15603a
[Tool] Patch test case due to changes in the template script
2021-06-04 18:17:47 -06:00
5f96d440ec
[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
2021-06-04 11:48:05 -06:00
ec203d3a5c
[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
2021-06-04 11:35:23 -06:00
2068291de0
[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
2021-06-04 11:32:49 -06:00
aa4e1f5f9a
[Test] Update test case which uses write_full_testbench openfpga shell script
2021-06-04 11:29:43 -06:00
ebe30fc070
[Test] Deploy write full testbench to multi-head configuration chain test case
2021-06-03 17:08:33 -06:00
1e9f6eb439
[Test] update configuration chain test to use new testbench
2021-06-03 15:53:27 -06:00
f1658cb735
[Test] Deploy blinking to test cases
2021-05-06 15:17:45 -06:00
8046b16c15
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
2021-04-21 14:04:34 -06:00
da95da933b
[Test] Add pin constraint file to map reset to correct FPGA pins
2021-04-17 15:04:26 -06:00
7172fc9ea1
[Test] Patch test for architecture using asynchronous DFFs
2021-04-16 20:48:37 -06:00
93be81abe1
[Test] Add test case for architecture using DFF with reset
2021-04-16 20:00:48 -06:00
a4893e27cf
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
2021-04-11 17:26:27 -06:00
d12a8a03fd
[Test] Update test case using yosys bram parameters
2021-03-16 19:52:17 -06:00
73b06256d0
[Test] Deploy the new yosys script supporting BRAM to regression tests
2021-03-16 16:52:59 -06:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
tangxifan
Ganesh Gore
AurelienAlacchi