tangxifan
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4add9781d5
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[Script] Add a new openfpga shell script for don't care bits outputting
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2021-10-05 19:13:50 -07:00 |
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tangxifan
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f32ffb6d61
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[Test] Bug fix
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2021-06-29 18:51:28 -06:00 |
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tangxifan
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56b0428eba
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[Misc] Bug fix
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2021-06-29 18:48:19 -06:00 |
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tangxifan
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c6089385b0
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[Misc] Bug fix
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2021-06-29 18:34:41 -06:00 |
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tangxifan
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5f5a03f17f
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[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
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2021-06-29 18:28:38 -06:00 |
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tangxifan
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4fb34642ca
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[Script] Add a new example script for global tile clock running full testbench
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2021-06-29 17:53:56 -06:00 |
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tangxifan
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9655bc35cb
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[Script] Bug fix due to the full testbench generation changes
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2021-06-29 17:04:19 -06:00 |
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tangxifan
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20faf82e64
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[Script] Rename example script
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2021-06-29 16:02:35 -06:00 |
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tangxifan
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01391fd81e
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[Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features
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2021-06-29 15:56:33 -06:00 |
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tangxifan
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4a623bec79
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[Script] Add example openfpga shell script to generate preconfigured fabric wrapper
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2021-06-27 19:55:40 -06:00 |
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tangxifan
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fae5e1dfdf
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[Script] Upgrade openfpga shell script with the new option '--embed_bitstream'
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2021-06-25 15:16:37 -06:00 |
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tangxifan
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b2c30e3103
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[Test] Bug fix in mcnc openfpga shell script
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2021-06-22 16:40:24 -06:00 |
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tangxifan
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96cb3081ab
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Update fix_device_route_chan_width_example_script.openfpga
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2021-06-18 09:51:16 -06:00 |
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tangxifan
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d40cf98c48
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[Test] Update test cases by using default net type in testbench generator
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2021-06-14 11:47:28 -06:00 |
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tangxifan
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d545069aac
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[Script] Bug fix
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2021-06-09 14:50:37 -06:00 |
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tangxifan
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4e3f589810
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[Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench'
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2021-06-09 13:53:28 -06:00 |
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tangxifan
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f9404dc97d
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[Script] Patch openfpga shell script due to missing a mandatory option in 'write_full_testbench'
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2021-06-09 11:55:25 -06:00 |
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tangxifan
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9adf94bfd3
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[Script] Update all the openshell scripts to deprecate 'write_verilog_testbench'
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2021-06-09 11:18:52 -06:00 |
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tangxifan
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be26c06673
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[Script] Update an example script to use 'write_preconfigured_fabric_wrapper' and 'write_preconfigured_testbench' in place of 'write_verilog_testbench'
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2021-06-09 10:41:22 -06:00 |
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tangxifan
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e9fa44cc25
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[Tool] Add fast configuration to the write bitstream command in example shell script
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2021-06-04 16:24:56 -06:00 |
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tangxifan
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f5e90c9467
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[Script] Update openfpga shell script with fast configuration option
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2021-06-04 11:28:10 -06:00 |
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tangxifan
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8fc90637e0
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[Script] Update write_full_testbench example script to support custom device layout in VPR
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2021-06-03 17:08:08 -06:00 |
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tangxifan
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51ca62a464
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[Script] Add example script for write_full_testbench command
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2021-06-03 15:48:59 -06:00 |
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tangxifan
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7dc7c1b4f5
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[Script] Add example openfpga shell script showing how to use 'report_bitstream_distribution' command
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2021-05-07 12:05:47 -06:00 |
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tangxifan
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f9fd444b86
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[Script] Add an write I/O mapping example script for openfpga shell
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2021-04-27 14:40:26 -06:00 |
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tangxifan
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09cc7f0007
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[Script] Enable constant net routing for heterogeneous FPGAs
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2021-04-23 20:44:36 -06:00 |
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tangxifan
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cbb7d41b6e
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[Script] Enable constant net routing for VTR benchmarks
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2021-04-23 14:15:13 -06:00 |
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tangxifan
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a16896054d
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[Script] Enable constant net routing for iwls benchmarks
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2021-04-22 19:16:32 -06:00 |
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tangxifan
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64163edbe6
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[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
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2021-04-19 16:15:25 -06:00 |
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tangxifan
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7018073e28
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[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
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2021-04-17 15:04:51 -06:00 |
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tangxifan
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c020333512
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Merge branch 'master' into dff_techmap
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2021-04-16 20:54:28 -06:00 |
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tangxifan
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2666726f36
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[Script] Remove clock routing from example openfpga shell script without ace
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2021-04-16 20:46:49 -06:00 |
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tangxifan
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23d08757cf
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[Script] Add example script without using ACE2
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2021-04-16 20:20:10 -06:00 |
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tangxifan
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43bf016576
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[Script] Add example openfpga shell script for iwls benchmark
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2021-04-16 16:09:47 -06:00 |
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tangxifan
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b469705819
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Merge branch 'master' into fpga_sdc_test
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2021-04-11 21:14:46 -06:00 |
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tangxifan
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07f6066c11
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[Script] Update timing unit in SDC example script
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2021-04-11 20:24:18 -06:00 |
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tangxifan
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94c4c817eb
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[Test] Expand sdc time unit test to sweep all the available units
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2021-04-11 20:14:09 -06:00 |
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tangxifan
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a4893e27cf
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[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
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2021-04-11 17:26:27 -06:00 |
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tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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145a80de43
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[Script] Add an openfpga shell script for heterogeneous fpga verification
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2021-03-23 15:35:34 -06:00 |
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tangxifan
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d050f1b746
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[Script] Enable fast bitstream generation for VTR benchmarks
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2021-03-22 12:54:36 -06:00 |
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tangxifan
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eca2a35612
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[Script] Add route chan width option to vtr openfpga script
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2021-03-20 22:00:09 -06:00 |
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tangxifan
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cb07848475
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[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
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2021-03-20 18:11:54 -06:00 |
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tangxifan
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deee7ba366
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[Script] Add example script to run vtr benchmarks
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2021-03-17 15:10:56 -06:00 |
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tangxifan
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e34380a654
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Merge branch 'master' into default_net_type
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2021-03-01 08:38:58 -07:00 |
Lalit Sharma
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ea4aee8cb2
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For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
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tangxifan
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b4b6ada06f
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[Script] Correct bugs in example scripts using default_net_type
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2021-02-28 16:31:44 -07:00 |
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tangxifan
|
8cc2c7d924
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[Script] Bug fix for default net type example script
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2021-02-28 12:35:44 -07:00 |
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tangxifan
|
0723b79bce
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[Script] Add example script for verilog default net type
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2021-02-28 12:29:56 -07:00 |
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tangxifan
|
ae05871b1f
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[Script] Remove default net type from an example script; Limit it to some test cases
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2021-02-28 12:19:14 -07:00 |