tangxifan
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abafeb01a8
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[Test] Rename test yml and try to patch if errors
|
2020-11-24 11:20:40 -07:00 |
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tangxifan
|
6ee5fce61f
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[Test] Fix if syntax errors
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2020-11-24 11:11:34 -07:00 |
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tangxifan
|
a6e55cbe94
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[Test] Try to fix the syntax error in if clauses
|
2020-11-24 11:07:10 -07:00 |
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tangxifan
|
5574c7b440
|
[Test] Add regression tests to Github Actions
|
2020-11-24 11:03:31 -07:00 |
|
tangxifan
|
04d84a12b5
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[Test] Rename build tests
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2020-11-24 10:43:17 -07:00 |
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tangxifan
|
6b9f236d81
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[Test] Specify paths to ccache files
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2020-11-24 10:37:15 -07:00 |
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tangxifan
|
43564c584d
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[Test] Add the matrix for compiler compatibility tests
|
2020-11-24 10:29:05 -07:00 |
|
tangxifan
|
0daa484134
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[Test] Remove wrong syntax about ccache
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2020-11-24 10:25:12 -07:00 |
|
tangxifan
|
0bb185f6a0
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[Test] Try to fix the problem on storing ccache results
|
2020-11-24 10:16:24 -07:00 |
|
tangxifan
|
3536f0baae
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[Test] Adapt regression tests scripts for github actions
|
2020-11-24 09:58:23 -07:00 |
|
tangxifan
|
dc164a0636
|
[Test] Remove unnecssary space that break CI
|
2020-11-24 09:38:18 -07:00 |
|
tangxifan
|
c257abe864
|
[Test] Add CMake and iVerilog version number output
|
2020-11-24 09:33:00 -07:00 |
|
tangxifan
|
121f628f6b
|
[Test] Add CXX and CC configuration
|
2020-11-24 09:31:25 -07:00 |
|
tangxifan
|
82954483b8
|
[Test] Bug fix in using MAKEFLAGS
|
2020-11-24 09:29:11 -07:00 |
|
tangxifan
|
88bf523bc8
|
[Test] Remove artifact uploading; focus on testing ccache
|
2020-11-24 09:19:09 -07:00 |
|
tangxifan
|
f417996b36
|
[Test] Add ccache to dependency
|
2020-11-23 22:57:19 -07:00 |
|
tangxifan
|
4d2f6bc656
|
[Test] Bug fix
|
2020-11-23 22:52:01 -07:00 |
|
tangxifan
|
703ba0b174
|
[Test] Enable ccache in cmake execution
|
2020-11-23 22:46:20 -07:00 |
|
tangxifan
|
814aa49a5b
|
[Test] Bug fix in github Actions script
|
2020-11-23 22:34:37 -07:00 |
|
tangxifan
|
6dbf22bc3d
|
[Test] Add artifact upload
|
2020-11-23 22:32:28 -07:00 |
|
tangxifan
|
d3e2dee215
|
[Test] Bug fix in github action script
|
2020-11-23 22:31:30 -07:00 |
|
tangxifan
|
433c259d91
|
[Test] Add ccache for compilation results to speed up CI
|
2020-11-23 22:28:17 -07:00 |
|
tangxifan
|
af21aa0522
|
[Test]Try env variable for parallel cmake build
|
2020-11-23 20:52:07 -07:00 |
|
tangxifan
|
7bd2622fd6
|
[Test] Try parallel build for Cmake in github actions
|
2020-11-23 20:50:19 -07:00 |
|
tangxifan
|
84c39315a5
|
[Test] Use example CMake build scripts from Github actions
|
2020-11-23 20:40:05 -07:00 |
|
tangxifan
|
de44e8c9d1
|
[Test] Bug fix for github actions
|
2020-11-23 20:24:18 -07:00 |
|
tangxifan
|
a95ddef90d
|
[Test] Bug fix in calling scripts for Github Actions
|
2020-11-23 20:22:59 -07:00 |
|
tangxifan
|
f2b6655550
|
[Test] Start porting to Github Actions with build test
|
2020-11-23 20:19:44 -07:00 |
|
tangxifan
|
c82f01b3ab
|
[Tool] Use conditional operator in signal initialization to eliminate all the warning messages
|
2020-11-23 15:50:23 -07:00 |
|
tangxifan
|
b857135f4e
|
[Doc] Add clarification about which cells are applicable for signal initialization
|
2020-11-23 15:19:15 -07:00 |
|
tangxifan
|
2b9a97729e
|
[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
|
2020-11-23 15:09:47 -07:00 |
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tangxifan
|
e644545f21
|
[Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors
|
2020-11-23 15:02:06 -07:00 |
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tangxifan
|
6ba02f35ca
|
Merge pull request #130 from antmicro/rr_graph_load_fix
Fix for rr graph loading by VPR
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2020-11-23 09:31:29 -07:00 |
Maciej Kurc
|
3d38e76c8f
|
Disabled printing segment ids for non-channel nodes.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
|
2020-11-23 17:07:28 +01:00 |
|
Maciej Kurc
|
b6728cf2d9
|
Added loading rr node segment indices
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
|
2020-11-23 14:53:50 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
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b78803a6bb
|
Merge pull request #129 from LNIS-Projects/dev
Generate Signal Initialization in Verilog Testbenches rather than HDL netlists
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2020-11-22 21:48:22 -07:00 |
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tangxifan
|
fd80cacaa3
|
[Flow] Add example script for behaviorial verilog generation
|
2020-11-22 21:14:10 -07:00 |
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tangxifan
|
617f7e3062
|
[Flow] disable signal initialization for behavioral verilog generation
|
2020-11-22 21:13:22 -07:00 |
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tangxifan
|
5eb04e6fff
|
[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
|
2020-11-22 20:53:32 -07:00 |
|
tangxifan
|
fd0e6814ea
|
[Doc] Update documentation about the pre-processing flags
|
2020-11-22 20:33:15 -07:00 |
|
tangxifan
|
3b2a4c5387
|
[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
|
2020-11-22 20:25:03 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
tangxifan
|
348872f8a4
|
[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
|
2020-11-22 16:12:28 -07:00 |
|
tangxifan
|
57a24570f5
|
[Tool] Move icarus and signal initialization options to testbench generator
|
2020-11-22 16:01:31 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
a00752938b
|
Merge pull request #127 from LNIS-Projects/dev
Bug fix for global clock port using physical tile pins
|
2020-11-17 15:56:08 -07:00 |
|
tangxifan
|
845436fa71
|
[Test] Add sequential benchmark for global tile clock test case
|
2020-11-17 14:34:54 -07:00 |
|
tangxifan
|
91b0dbbaa2
|
[Script] Add example openfpga shell run script when using global tile clocks
|
2020-11-17 14:33:12 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
3a80af3408
|
Merge pull request #126 from LNIS-Projects/dev
Multiple Bug Fixes
|
2020-11-13 16:44:58 -07:00 |
|
tangxifan
|
3f91b8433e
|
[Tool] Change the i/o numbering to the clockwise sequence
|
2020-11-13 15:00:25 -07:00 |
|
tangxifan
|
088198c861
|
[Tool] enhance error checking in fabric key parser
|
2020-11-13 10:56:00 -07:00 |