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OpenFPGA
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Aram Kostanyan
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
tangxifan
2baf3ddd2f
[Test] Add test cases for 'report_bitstream_distribution' command
2021-05-07 12:06:24 -06:00