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OpenFPGA
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tangxifan
da3f9ccb80
[Test] Truncating counter designs in each task
2022-02-14 12:22:19 -08:00
tangxifan
0268814fc6
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
2022-02-14 12:20:56 -08:00