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OpenFPGA
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6,304 Commits 70 Branches 8 Tags 105 MiB
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6304 Commits

Author SHA1 Message Date
tangxifan 3c6a4d34d8 [core] code format 2023-04-24 13:36:59 +08:00
tangxifan 715765d81b [core] code complete for top testbench generator on ccffv2 upgrades 2023-04-24 13:34:44 +08:00
tangxifan 667d9df028 [core] developing testbench generator for ccff v2 2023-04-24 11:36:21 +08:00
tangxifan 1ba3c56cf3 [core] code format 2023-04-23 16:49:19 +08:00
tangxifan ba90f5020b [core] fixed some bugs which cause netlist generation failed 2023-04-23 16:48:14 +08:00
tangxifan 28b7a12f68 [core] code format 2023-04-23 14:31:35 +08:00
tangxifan bd511ba515 [core] fixed syntax errors 2023-04-23 14:26:08 +08:00
tangxifan 592765af48 [core] code complete for upgrading netlist generator w.r.t. ccff v2 2023-04-23 13:57:37 +08:00
tangxifan 5500b9a289 [core] upgrading netlist generator 2023-04-22 16:27:27 +08:00
tangxifan 02e964b16f [test] add a new test case for ccffv2 2023-04-22 15:41:19 +08:00
tangxifan ea8ae29b53 [core] code format 2023-04-22 15:12:38 +08:00
tangxifan 297a23dee7 [core] fixed syntax errors 2023-04-22 15:09:39 +08:00
tangxifan 5e8e982334 [core] finished developing checkers 2023-04-22 12:44:34 +08:00
tangxifan 79b903647d
Merge pull request #1135 from lnis-uofu/dependabot/submodules/yosys-plugins-137606e 
Bump yosys-plugins from `96a0853` to `137606e`
 2023-04-22 12:21:58 +08:00
tangxifan cd8d5de348
Merge pull request #1137 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-04-22 12:04:25 +08:00
tangxifan f70cc32824 [core] developing checkers for configuration protocol w.r.t. the programming clocks 2023-04-22 08:46:36 +08:00
github-actions[bot] 14892a6146 Updated Patch Count 2023-04-22 00:02:24 +00:00
tangxifan 95f97115ee
Merge pull request #1136 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-90ee6e6 
Bump vtr-verilog-to-routing from `d70659f` to `90ee6e6`
 2023-04-21 23:47:14 +08:00
tangxifan dba449f42a [core] code complete for parsers 2023-04-21 23:45:35 +08:00
tangxifan 6e44f3f5fc [core] developing ccff_v2 parsers 2023-04-21 17:01:51 +08:00
tangxifan 76a553e7bc [doc] supplementary description 2023-04-21 15:23:51 +08:00
tangxifan c220438c42 [doc] adding new syntax that supports separated clocks for multi-head configuration chains 2023-04-21 15:21:34 +08:00
dependabot[bot] 7694f71055
Bump vtr-verilog-to-routing from `d70659f` to `90ee6e6` 
Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `d70659f` to `90ee6e6`.
- [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases)
- [Commits](d70659f424...90ee6e663a)

---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-04-21 06:58:57 +00:00
dependabot[bot] 82f526fc61
Bump yosys-plugins from `96a0853` to `137606e` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `96a0853` to `137606e`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](96a0853eba...137606ebfa)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-04-21 06:58:52 +00:00
tangxifan 3905d14fd3
Merge pull request #1134 from lnis-uofu/xt_doc_hotfix 
[doc] fix broken links in the Clock Network file format
 2023-04-21 14:31:22 +08:00
tangxifan 081620055b [doc] fix broken links in the Clock Network file format 2023-04-21 13:58:13 +08:00
tangxifan c58f890420
Merge pull request #1133 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-04-21 09:31:03 +08:00
github-actions[bot] 074e8f5150 Updated Patch Count 2023-04-21 00:02:29 +00:00
tangxifan 81428090b3
Merge pull request #1090 from lnis-uofu/xt_clk_arch 
Programmable Clock Architecture Support
 2023-04-20 22:27:02 +08:00
tangxifan 509f5eb6dc [doc] add documentation about clock network description file 2023-04-20 17:06:53 +08:00
tangxifan 9756bfe0ca [doc] document newly added commands for programmable clock arch support 2023-04-20 15:27:28 +08:00
tangxifan aeeee6d8bd [core] code format 2023-04-20 15:07:54 +08:00
tangxifan 087636cefa [test] deploy new test to regression tests 2023-04-20 15:06:47 +08:00
tangxifan 40598d25a3 [core] fixed a bug which causes multi-clock programmable network failed in routing 2023-04-20 15:05:45 +08:00
tangxifan fba0a83679 [test] debugging 2-clock network 2023-04-20 14:44:01 +08:00
tangxifan 02b02d18a5 [test] fixed a bug in clock arch 2023-04-20 11:35:36 +08:00
tangxifan b242fd97d6 [test] adding new arch and testcase for 2-clock network 2023-04-20 11:31:49 +08:00
tangxifan 03cb664049 [test] now clock network example script supports multiple clocks 2023-04-20 10:56:36 +08:00
tangxifan 7d333b3669 [test] add a new test for clock network: validate full testbench is working 2023-04-20 10:36:08 +08:00
tangxifan 1f9c1fe7e1 [test] clean up clock network task config 2023-04-20 10:31:22 +08:00
tangxifan b10782de72
Merge branch 'master' into xt_clk_arch 2023-04-20 10:22:34 +08:00
tangxifan 02a0f18751
Merge pull request #1132 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-04-20 10:09:58 +08:00
github-actions[bot] 87b3f9d828 Updated Patch Count 2023-04-20 00:02:33 +00:00
tangxifan 928c7d5736 Merge branch 'master' into xt_clk_arch 2023-04-19 22:17:33 +08:00
tangxifan 30a9f6fbb6
Merge pull request #1128 from lnis-uofu/vtr_upgrade 
Upgrade VTR to latest version in its 'openfpga' branch
 2023-04-19 21:52:35 +08:00
tangxifan 9690cea115 [core] fix clang syntax 2023-04-19 15:46:42 +08:00
tangxifan 5db2741c0a
Merge branch 'master' into vtr_upgrade 2023-04-19 11:20:04 +08:00
tangxifan 7d13faffe9 [script] now split make checkout and make compile 2023-04-19 11:19:27 +08:00
tangxifan c7203cd6e6 [script] revert back the old make all recipe 2023-04-19 11:11:24 +08:00
tangxifan cb4512b925 [core] code format 2023-04-19 11:10:42 +08:00