Commit Graph

1853 Commits

Author SHA1 Message Date
tangxifan 1f092171f2 Merge branch 'refactoring' into dev 2020-03-09 09:45:31 -06:00
tangxifan d61ae5561b start cleanup the documentation for openfpga shell 2020-03-09 09:44:19 -06:00
tangxifan 94d9b6e615 Merge branch 'refactoring' into dev 2020-03-09 09:35:59 -06:00
tangxifan 3aca7b498c Show help desk when a command is called inside shell without satisfying the dependency 2020-03-09 09:34:21 -06:00
tangxifan 2f38b5cbc2 Merge branch 'refactoring' into dev 2020-03-08 16:23:20 -06:00
tangxifan aff73bdd74 deployed edge sorting and make it as an option to link_arch command 2020-03-08 15:59:53 -06:00
tangxifan b80e26e711 update bitstream generator to use sorted edges 2020-03-08 15:36:47 -06:00
tangxifan 5558932762 use sorted edges in building routing modules 2020-03-08 15:31:41 -06:00
tangxifan 7a7f8374b3 start deploying edge sorting in uniquifying SB modules 2020-03-08 15:24:34 -06:00
tangxifan f9499afe04 remove unused variable 2020-03-08 15:00:01 -06:00
tangxifan 0c7aa2581d update vpr8 version with hotfix on undriven pins in GSB 2020-03-08 14:58:56 -06:00
tangxifan b219b096ee hotfix on removing dangling inputs from GSB, which are CLB direct output 2020-03-08 13:54:49 -06:00
tangxifan b2534f1a09 Merge branch 'refactoring' into dev 2020-03-07 23:31:45 -07:00
tangxifan 0fbf3fca41 start developing edge sorting inside RRGSB 2020-03-07 23:30:55 -07:00
tangxifan 8b40ca2990 Merge branch 'refactoring' into dev 2020-03-07 17:54:13 -07:00
tangxifan ca92c2717f bug fix for tile directs 2020-03-07 16:00:32 -07:00
tangxifan e48c2b116d bug fixing for duplicated grid pin names 2020-03-07 15:46:12 -07:00
tangxifan 37423729ec bug fixing for naming the duplicated pins 2020-03-07 15:44:57 -07:00
tangxifan 3eeac94a6e Merge branch 'refactoring' into dev 2020-03-06 20:58:07 -07:00
tangxifan c36c302052 looks like tileable routing is working 2020-03-06 17:16:53 -07:00
tangxifan f54f46483b start debugging tileable rr_graph generator 2020-03-06 17:02:22 -07:00
tangxifan 5be118d695 tileable rr_graph builder ready to debug 2020-03-06 16:18:45 -07:00
tangxifan 245a379c4f start plug in tileable rr_graph builder 2020-03-06 16:03:00 -07:00
tangxifan 3eb59d201f adapt top function of tileable rr_graph builder 2020-03-06 15:24:26 -07:00
tangxifan 441a307100 add routing chan width corrector to rr_graph builder utils 2020-03-06 14:54:40 -07:00
tangxifan 441de12936 adapt Fc in gsb connection builder to use VPR8 Fc builder 2020-03-06 14:43:12 -07:00
tangxifan ee4d5e46a0 Merge branch 'refactoring' into dev 2020-03-05 21:25:36 -07:00
tangxifan 8d350ee22f adapt tileable rr_graph edge builder to rr_graph object 2020-03-05 20:50:21 -07:00
tangxifan 328488f357 adapt chan rr node builder to use rr_graph obj 2020-03-05 20:15:16 -07:00
tangxifan 3e3a523926 Merge branch 'refactoring' into dev 2020-03-05 17:48:43 -07:00
tangxifan 5067dd846e adapting channel rr_node builder for tileable rr_graph 2020-03-05 17:47:48 -07:00
tangxifan 850788eace adapt tileable rr_graph node builder for rr_graph object 2020-03-05 17:15:49 -07:00
tangxifan 5dcffb1a6e Merge branch 'refactoring' into dev 2020-03-05 15:36:16 -07:00
tangxifan de62ce8872 add node builder for tileable rr_graph builder 2020-03-05 15:34:04 -07:00
tangxifan 646ee90937 bring tileable gsb builder for rr_graph online 2020-03-04 18:19:53 -07:00
tangxifan 4455615980 adapt tileable routing channel detail builder 2020-03-04 14:21:35 -07:00
tangxifan 6e83154703 move rr_gsb and rr_chan to tileable rr_graph builder 2020-03-04 14:14:28 -07:00
tangxifan 4b7d2221d1 adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr 2020-03-04 13:55:53 -07:00
tangxifan 524798799c start adapting tileable rr_graph builder. Bring channel node detail data structure online 2020-03-04 11:21:34 -07:00
AurelienUoU aed3b01800 Directlist extension bug fix 2020-03-04 09:09:06 -07:00
tangxifan 9f13d3bc23 Merge branch 'refactoring' into dev 2020-03-03 12:31:20 -07:00
tangxifan 7fcd27e000 now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer 2020-03-03 12:29:58 -07:00
tangxifan 3241d8bd37 put analysis sdc writer online. Minor bug in redudant '/' to be fixed 2020-03-02 19:54:18 -07:00
tangxifan 037c7e5c43 adapt top-level function for analysis SDC writer 2020-03-02 17:58:44 -07:00
tangxifan 24f7416c71 adapt analysis SDC writer for grids 2020-03-02 17:15:01 -07:00
tangxifan 6474183539 adapt analysis SDC writer for routing modules 2020-03-02 14:29:58 -07:00
tangxifan 543cff58b9 start porting analysis SDC writer 2020-03-02 13:44:08 -07:00
tangxifan 7befcaba57 Merge branch 'refactoring' into dev 2020-03-02 11:22:58 -07:00
tangxifan a17c14c363 clean-up command addition and add fabric bitstream building to sample script 2020-03-02 10:39:19 -07:00
tangxifan 9fe8ff51f9 Merge branch 'refactoring' into dev 2020-02-29 15:19:52 -07:00